Memory Chip With Time-Segmented Circuits for TFT Leakage Control
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Solution Overview
Problem
Thin film transistor (TFT) memory devices face issues with high resistance between sources and drains, low mobility, and poor uniformity, making them unsuitable for designing amplifiers and memory circuit structures.
Innovation Solution
A memory chip design incorporating a first encoding device and memory device with synchronized memory circuits, controlled by enabling signals and pulse signals, reducing resistance and leakage currents, and optimizing area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If TFT memory device is used, then manufacturing is simpler, but resistance between sources and drains increases and mobility decreases
Solution Approach 1:
The memory device is divided into multiple independent memory circuits (first memory circuit, second memory circuit, etc.), each capable of operating independently. This segmentation allows optimization of each circuit's performance while maintaining overall manufacturing simplicity of the TFT-based system.
Solution Approach 2:
The patent transitions from a single memory circuit to a multi-circuit architecture operating in different time periods. The first memory circuit operates during a first period, while the second memory circuit operates during a second period, effectively adding a temporal dimension to the memory operation.
2Device complexity
If single memory circuit is used, then device complexity is lower, but area efficiency and leakage current reduction are limited
Solution Approach 1:
The memory device employs periodic operation where the first memory circuit operates during a first period and the second memory circuit operates during a second period. This periodic action allows the same physical infrastructure to serve multiple functions at different times, improving area efficiency without proportionally increasing device complexity.
Solution Approach 2:
Multiple memory circuits share common control structures and operational mechanisms. The same control circuitry and architecture patterns are reused across different memory circuits, allowing the system to achieve higher capacity and area efficiency while keeping the incremental complexity manageable through universal design.
3Speed
If memory circuits operate simultaneously, then data access speed is faster, but leakage current increases
Solution Approach 1:
Memory circuits are activated in periodic intervals rather than simultaneously. The first memory circuit is activated during a first period, and the second memory circuit is activated during a second period. This periodic activation reduces simultaneous leakage current while maintaining acceptable data access speed through sequential operation.
Solution Approach 2:
The control circuitry prepares and activates memory circuits in advance according to the required operation sequence. By preliminarily determining which memory circuit should operate next and preparing it accordingly, the system optimizes the timing of activation to minimize leakage while ensuring data is ready when needed.
Data Source
AI summary
A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.