Two-Way Time Sync Packet Offload for Line-Rate Network Clocks
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Solution Overview
Problem
Existing clock synchronization methods in network devices, particularly those using two-way time synchronization protocols, lead to CPU overload and delays due to high processing demands, compromising time synchronization services and making it difficult to serve multiple followers effectively.
Innovation Solution
Offload two-way time synchronization protocol packet processing to a network device's packet processing pipeline, such as a network interface controller (NIC) or switch, allowing processing at line rate without host CPU involvement, using hardware-based match-and-action processing to handle time synchronization packets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two-way time synchronization protocol packet processing is performed by the host CPU, then time synchronization can be achieved, but CPU overload and delays occur due to high processing demands
Solution Approach 1:
The patent extracts the time synchronization packet processing function from the host CPU and relocates it to the network device's packet processing pipeline. This is achieved by implementing a dedicated hardware module within the network device that can independently process PTP packets, thereby relieving the CPU of this time-critical task while maintaining synchronization accuracy.
Solution Approach 2:
The patent introduces an intermediary hardware module in the network device that acts as a mediator between the network interface and the host CPU. This module preprocesses time synchronization packets, performing critical timing operations in hardware before passing processed data to the CPU, thus reducing CPU workload while preserving synchronization precision.
2Reliability
If two-way time synchronization protocol packet processing is performed by the host CPU, then time synchronization can be achieved, but delays occur due to high processing demands
Solution Approach 1:
The patent replaces the software-based CPU processing mechanism with a hardware-based packet processing pipeline. By implementing time synchronization packet handling in hardware (using dedicated circuits and logic gates), the system achieves faster processing speeds and reduced latency while maintaining the accuracy required for precise clock synchronization.
Solution Approach 2:
The patent performs preliminary processing of time synchronization packets in the network device's hardware pipeline before the packets reach the host CPU. Critical timing operations such as packet timestamping and initial validation are completed in advance in hardware, reducing the time the CPU needs to spend on these operations and minimizing overall synchronization delays.
3Productivity
If two-way time synchronization protocol packet processing is offloaded to packet processing pipeline, then processing at line rate is achieved, but device complexity increases
Solution Approach 1:
The patent designs the packet processing pipeline to handle multiple types of network traffic using a unified hardware architecture. The same processing infrastructure that handles regular data packets is extended to also process time synchronization packets, allowing the system to achieve line-rate processing without adding separate dedicated hardware paths for each protocol type.
Solution Approach 2:
The patent merges the time synchronization packet processing functionality with the existing packet processing pipeline of the network device. By integrating PTP packet handling into the general-purpose data plane, the system achieves high-speed processing while avoiding the complexity of a completely separate synchronization processing subsystem.
4Reliability
If two-way time synchronization protocol packet processing is performed by host CPU, then synchronization with multiple clients can be maintained, but CPU overload prevents effective service to multiple followers
Solution Approach 1:
The patent enables the network device to self-service time synchronization packet processing through its own internal hardware pipeline, without requiring host CPU intervention for each packet. The network device independently handles reception, processing, and transmission of synchronization packets, allowing it to serve multiple clients simultaneously without CPU bottlenecks.
Solution Approach 2:
The patent extracts the multi-client synchronization handling capability from the host CPU and embeds it directly in the network device's hardware. This allows the network device to manage multiple synchronization clients independently through parallel hardware processing paths, eliminating the CPU's capacity limitations when serving numerous followers.
Data Source
AI summary
In one embodiment, a network device includes a network interface to share time synchronization packets with at least one remote device over a network, a hardware clock to maintain a clock time, and packet processing circuitry to process the time synchronization packets according to a two-way time synchronization protocol in order to cause clock synchronization between the hardware clock and at least one clock of the at least one remote device.