Time Synchronization Device Using Segmented Counters for IEEE 1588 Precision
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Solution Overview
Problem
Timestamp counters with limited bit lengths in chips can only provide time values within a short period, making it impossible to obtain time-of-day (TOD) information for precise synchronization with a master device according to the IEEE 1588 precision time protocol.
Innovation Solution
A time synchronization device and method that utilize a packet processing circuit with an N-bit timestamp counter, a time counting circuit, and a processor to calculate offset values, adjustment values, and quotient values, allowing the determination of TOD at packet transmission or reception, even with limited counter values, by using multiple packet exchanges and a phase-locked loop circuit for precise time synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a timestamp counter with limited bit length (e.g., 32-bit) is used in a chip, then the device complexity is reduced and manufacturing is easier, but the time counting range is limited to a short period (e.g., 4.29 seconds) and time-of-day (TOD) information cannot be obtained
Solution Approach 1:
The patent divides the time measurement function into two independent parts: a timestamp counter with limited bit length (e.g., 32-bit) for precise short-term time counting, and a separate TOD counter for long-term time tracking. The timestamp counter handles packet timing within its limited range, while the TOD counter accumulates time over extended periods, resolving the contradiction between manufacturing simplicity and extended time range.
Solution Approach 2:
The patent introduces an intermediary calculation process that combines the timestamp counter value with the TOD counter value to achieve extended time measurement. The processor calculates the receiving time by adding the timestamp counter value (for precision) to the TOD counter value (for extended range), effectively extending the measurement range without requiring a high-bit counter.
2Device complexity
If a timestamp counter with limited bit length is used, then the device complexity is reduced, but the measurement precision for time-of-day (TOD) is lost
Solution Approach 1:
The patent segments the time measurement system into two specialized counters: a timestamp counter for precise packet timing and a TOD counter for accurate time-of-day tracking. Each counter is optimized for its specific function, maintaining measurement precision while keeping individual component complexity low.
Solution Approach 2:
The patent merges the outputs of the timestamp counter and TOD counter through a calculation process to produce the final receiving time value. This combination preserves the precision of the timestamp counter while incorporating the time-of-day accuracy of the TOD counter, achieving both precision and simplicity.
3Measurement precision
If a high-bit timestamp counter is used to provide TOD information, then the time measurement range and precision are improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
Instead of using a single high-bit counter, the patent segments the function into two separate counters with appropriate bit lengths for their specific purposes. This segmentation achieves the required measurement precision and range while keeping each counter's complexity manageable and manufacturing costs lower.
Solution Approach 2:
The patent uses a copy approach where the timestamp counter value is combined with the TOD counter value to create an extended time measurement. This copying and combining method achieves high-precision time measurement without requiring a single complex high-bit counter.
Data Source
AI summary
A time synchronization device performs a time synchronization process with a device that provides first and second time values. The time synchronization device includes a packet processing circuit, a time counting circuit, and a processor. The packet processing circuit includes a timestamp counter having an N-bit length, and the packet processing circuit provides first to third time counting values. The processor calculates the first offset value based on the first and second time values and the first and second time counting values; calculates the first adjustment value based on the first offset value and the reciprocal of the frequency of the time counting circuit; calculates a second quotient value and a second remainder value based on the first adjustment value and the N-bit length; and calculates the receiving time of the second synchronization packet based on the N-bit length, the second quotient value, and the third time counting value.