Time-Triggered Computer Diagnostics With Cross-Checked Self-Tests
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Solution Overview
Problem
Conventional time-triggered computer systems face challenges in achieving comprehensive diagnostic coverage during Built-In Self-Tests (BISTs) within the Process Safety Time (PST) or Fault Tolerant Time Interval (FTTI) without disrupting normal system operation, and there is uncertainty in detecting processor failures using dynamic switches.
Innovation Solution
A time-triggered computer system design where multiple processors perform and verify self-tests independently, comparing results to ensure accurate completion of Power-On Self-Tests (POSTs) and BISTs, and enter a Fail-Safe State if any processor fails, without requiring processor resets during normal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If comprehensive BISTs are performed within PST/FTTI, then diagnostic coverage is improved, but system operation is disrupted
Solution Approach 1:
The system divides self-test execution into separate processor segments (first processor performs first BISTs, second processor performs second BISTs) allowing parallel operation. This segmentation enables comprehensive diagnostic coverage while maintaining system operation continuity, as each processor can independently execute tests without halting the entire system.
Solution Approach 2:
The patent implements continuous self-testing by having processors perform BISTs during normal operation without stopping system functions. The useful action of system operation continues uninterrupted while diagnostic actions are performed concurrently by dedicated processor resources.
2Difficulty of detecting and measuring
If dynamic switches are used to detect processor failures, then detection capability is improved, but reliability is reduced due to uncertainty
Solution Approach 1:
The system implements feedback mechanisms where processors exchange test result data through communication channels. Each processor performs self-tests and sends results to other processors, which verify the results and provide feedback. This closed-loop feedback system eliminates uncertainty in failure detection by cross-validating results independently.
Solution Approach 2:
Communication channels and message passing mechanisms serve as intermediaries between processors for transmitting test data and failure information. This intermediary system allows reliable failure detection without direct processor interference, maintaining system stability while improving detection capability through structured information exchange.
3Reliability
If processor resets are performed during BISTs, then test completeness is improved, but system disruption increases
Solution Approach 1:
The patent extracts the processor reset operation from the normal BIST execution flow. Instead of resetting processors during routine BISTs, the system performs non-intrusive tests during operation and only initiates resets when actual failures are detected and confirmed through inter-processor verification. This separation maintains test completeness while minimizing unnecessary system disruptions.
Solution Approach 2:
The system performs preliminary diagnostic checks and data exchanges before committing to processor resets. Processors exchange test result data and verify failures before initiating reset sequences, ensuring that resets are only performed when absolutely necessary. This preliminary verification action reduces unnecessary disruptions while maintaining comprehensive testing.
Data Source
AI summary
Time-triggered computer systems, methods and computer programs are disclosed. A time-triggered computer system comprises at least one first processor that is adapted to: perform at least one first Power-On Self-Test, POST, and/or at least one first Built-In Self-Test, BIST and transmit first data, that is indicative of results of at least one said first POST and/or said first BIST, to at least one second processor; and at least one second processor that is adapted to: compare the first data with second data, that is data indicative of expected results from at least one said first POST and/or said first BIST and responsive to the comparison, determine if at least one said first POST and/or first BIST has passed or failed.