Timed Data Transfer for Memory Sub-Systems
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Solution Overview
Problem
Traditional memory sub-systems face inefficiencies due to throttling of input/output activities caused by cache buffer memory limitations, leading to increased power-fail hold-up requirements and command collisions, which result in higher system costs and data blocking issues.
Innovation Solution
Implementing a queuing mechanism that allows commands to be accepted without immediate data recording, mapping them to media units and transferring data just in time for execution, reducing the need for large cache buffer memory and power-fail hold-up circuits by enabling non-blocking command processing and out-of-order execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional caching architecture is used to isolate host system from memory sub-system, then write latency is reduced, but cache buffer memory size must be increased leading to higher system costs
Solution Approach 1:
The patent applies preliminary action by pre-fetching data from the memory sub-system into the cache buffer before the host system actually needs it. The data transfer is initiated based on predicted future access patterns, allowing the cache to be populated in advance. This reduces write latency when data is needed while avoiding the need for excessively large cache buffers, as data is loaded proactively rather than reactively.
Solution Approach 2:
The patent implements dynamics by making the cache buffer size and data transfer timing adaptive rather than static. The system dynamically adjusts the amount of data to prefetch and the timing of transfers based on actual host access patterns, memory sub-system availability, and current system load. This dynamic approach allows the cache to efficiently handle varying workloads without requiring a permanently large buffer.
2Productivity
If large cache buffer memory is used to handle write workloads, then command processing capability is improved, but power-fail hold-up circuit requirements increase
Solution Approach 1:
The patent applies periodic action by implementing scheduled, periodic data transfers from the memory sub-system to the cache buffer rather than continuous transfers. Data is fetched in periodic batches based on timers or scheduled intervals, allowing the system to maintain adequate cache levels while minimizing the duration that large amounts of data reside in the cache. This reduces the energy storage requirements for power-fail protection since the cache doesn't need to continuously hold large datasets.
Solution Approach 2:
The patent implements discarding and recovering by selectively evicting data from the cache buffer when it is no longer predicted to be needed, and recovering it later through prefetching when required. This dynamic management allows the cache to maintain smaller average sizes while still providing high productivity, as data is kept in the cache only for the minimum necessary duration, thereby reducing power-fail hold-up requirements.
3Productivity
If data is transferred immediately upon receiving write commands, then host write streams are blocked, but data transfer efficiency is reduced
Solution Approach 1:
The patent applies preliminary action by initiating data transfers before the host system completes issuing all write commands. The system starts transferring data based on the first received commands while the host continues to issue additional commands without blocking. This overlapping of command issuance and data transfer operations increases throughput while managing transfer timing to avoid excessive delays.
Solution Approach 2:
The patent implements continuity of useful action by maintaining continuous data transfer operations alongside continuous command processing. Rather than pausing command acceptance to complete transfers, the system sustains both operations simultaneously through parallel processing and background data transfers. This ensures neither host write streams nor data transfer efficiency is significantly compromised.
Data Source
AI summary
A memory sub-system configured to schedule the transfer of data from a host system for write commands to reduce the amount and time of data being buffered in the memory sub-system. For example, after receiving a plurality of streams of write commands from a host system, the memory sub-system identifies a plurality of media units in the memory sub-system for concurrent execution of a plurality of write commands respectively. In response to the plurality of commands being identified for concurrent execution in the plurality of media units respectively, the memory sub-system initiates communication of the data of the write commands from the host system to a local buffer memory of the memory sub-system. The memory sub-system has capacity to buffer write commands in a queue, for possible out of order execution, but limited capacity for buffering only the data of a portion of the write commands that are about to be executed.