Timed Hardware IP Unlocking for Secure Testing
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Solution Overview
Problem
Existing hardware intellectual property (IP) protection methods fail to securely allow testing of hardware IPs without revealing the unlocking key, making them vulnerable to piracy and reverse engineering, especially during untrusted facility testing.
Innovation Solution
The Timed Unlocking and Locking of hardware IPs (TULIP) framework provides a scalable, secure, and lightweight solution by implementing a state space obfuscation technique that temporarily unlocks hardware IPs for a predetermined period, using a timer FSM and obfuscation finite state machines to enable testing without exposing the functional key.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If design obfuscation is applied to protect hardware IPs, then security against piracy and reverse engineering is improved, but testing of the locked IPs requires sending the unlocking key to untrusted entities which leads to key exposure and abuse
Solution Approach 1:
The patent segments the unlocking key into multiple key components that are distributed across different locations or entities. Each key component alone is insufficient to unlock the IP, but collectively they can restore functionality. This segmentation prevents complete key exposure even if some components are compromised during testing.
Solution Approach 2:
The patent introduces a trusted intermediary entity or mechanism that manages the distribution and verification of key components. This intermediary coordinates between the IP owner and testing entities, ensuring that key components are shared securely without direct exposure to untrusted parties.
2Ease of operation
If the unlocking key is sent to untrusted testing entities for testing locked IPs, then testing functionality is enabled, but the security protection is compromised due to potential abuse and piracy
Solution Approach 1:
By dividing the unlocking key into multiple components distributed to different entities, the patent enables testing functionality while ensuring that no single untrusted entity receives the complete key, thus maintaining security protection against abuse and piracy.
Solution Approach 2:
The patent implements dynamic key management where key components can be temporarily provided for testing purposes and then revoked or invalidated. This allows flexible testing capability while maintaining the ability to revoke access if security concerns arise.
3Ease of operation
If permanent unlocking is applied to allow testing of hardware IPs, then testing access is improved, but the IP remains vulnerable to unauthorized use after testing
Solution Approach 1:
The patent implements temporary or time-limited unlocking mechanisms that provide testing access only for specified durations or under specific conditions. After the testing period expires or conditions are no longer met, the IP automatically re-locks, preventing ongoing unauthorized use while maintaining testing capability during the authorized period.
Solution Approach 2:
The patent employs periodic re-authentication or re-keying mechanisms where the IP must periodically verify the legitimacy of its operation. This creates intervals where unauthorized use can be detected and prevented, while allowing legitimate testing to proceed during authorized periods.
Data Source
AI summary
The present disclosure provides systems and methods for timed unlocking and locking of hardware intellectual properties obfuscation. One such method includes determining whether received key inputs match a functional key sequence of an integrated circuit or a test key sequence of the integrated circuit; permanently enabling operation of the integrated circuit responsive to the received key inputs being determined to be a functional key sequence for permanently enabling operation of the integrated circuit; temporarily enabling operation of the integrated circuit responsive to the received key inputs being determined to be the test key sequence for temporarily enabling operation of the integrated circuit to perform testing of the functionality and disable thereafter; and locking sequential logic and combinational logic of the integrated circuit if the received key inputs are determined to not be either the functional key sequence or the test key sequence. Other systems and methods are also provided.