Timed Level Shifter Circuit for High-Speed MOS Reliability
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Solution Overview
Problem
The existing level shifter designs, such as those disclosed by Wen-Tai Wang et al., face reliability issues due to the possibility of voltage exceeding the withstand voltage of low breakdown voltage MOS transistors, leading to degradation and reduced reliability during high-speed operations.
Innovation Solution
The proposed level shifter incorporates high breakdown voltage PMOS and depletion NMOS transistors in conjunction with low breakdown voltage NMOS transistors, utilizing a timing control unit to generate specific control signals that manage the conduction states of these transistors, preventing excessive voltage application to the low breakdown voltage NMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed operation is achieved using low breakdown voltage MOS transistors, then operation speed is improved, but voltage exceeding withstand voltage causes breakdown and deterioration of the transistors, degrading reliability
Solution Approach 1:
The timing control unit generates control signals in advance to turn off the low breakdown voltage NMOS transistors before high voltage is applied to them. This preliminary action prevents voltage exceeding withstand voltage from being applied to the transistors, thereby preventing breakdown and deterioration while maintaining high-speed operation capability
Solution Approach 2:
The timing control unit monitors the state of high breakdown voltage transistors and dynamically adjusts the control signals to low breakdown voltage NMOS transistors accordingly. This feedback mechanism ensures that low breakdown voltage transistors are turned off at the appropriate timing to avoid voltage breakdown, maintaining both high-speed operation and reliability
2Loss of energy
If voltage difference between internal voltage and external voltage increases due to lower internal voltage, then power consumption is reduced, but level shifter reliability degrades due to large voltage difference between input and output voltage
Solution Approach 1:
The level shifter is divided into multiple transistor stages with different breakdown voltage characteristics. High breakdown voltage PMOS and depletion NMOS transistors handle the high voltage side, while low breakdown voltage NMOS transistors handle the low voltage side. This segmentation allows the level shifter to accommodate large voltage differences while protecting sensitive low voltage transistors from breakdown
Solution Approach 2:
High breakdown voltage depletion NMOS transistors serve as intermediary elements between the high voltage power supply and low voltage NMOS transistors. These intermediary transistors isolate the low breakdown voltage transistors from excessive voltage, enabling the level shifter to operate with large voltage differences between input and output while maintaining reliability
Data Source
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AI summary
A level shifter includes high breakdown voltage first and second PMOS transistors (P1, P2), high breakdown voltage first and second depletion NMOS transistors (NA1, NA2) having gates respectively supplied with first and second control signals (IN1, IN2), low breakdown voltage first and second NMOS transistors (N1, N2) having gates respectively supplied with third and fourth control signals (IN3, IN4), and a timing control unit (12, 13) that generates the first control signal (IN1) and the third control signal (IN3) different from the inverted signal of an input signal (IN), and generates the second control signal (IN2) and the fourth control signal (IN4) different from the non-inverted signal of the input signal (IN).