Timed Mailbox for Multiprocessor Resource Latency

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Solution Overview

Problem

Conventional multiprocessor platforms face inefficiencies in shared resource utilization due to synchronization issues and latency problems, particularly when using semaphore and mailbox mechanisms, which lead to reduced performance and increased task latency.

Innovation Solution

A timed mailbox system is introduced, where a timer issues a warning signal in advance to inform processors when a shared resource will be available, allowing for minimal latency and improved resource utilization without requiring additional hardware modifications to the operating system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional mailbox mechanism is used to notify processors of shared resource availability, then resource synchronization is achieved, but task latency increases due to interrupt handling overhead

Engineering Contradiction:
Improveresource synchronizationVSAvoidtask latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The timer issues a warning signal in advance before the shared resource actually becomes available. This preliminary notification allows the first processor to prepare for resource acquisition ahead of time, reducing the actual waiting time when the resource becomes available. The warning signal is issued at a predetermined time calculated based on the expected resource availability time.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If processors lock the bus to prevent semaphore access errors, then data integrity is maintained, but shared resource utilization decreases

Engineering Contradiction:
Improvedata integrityVSAvoidshared resource utilization
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The invention extracts the critical section protection mechanism from the bus locking approach. Instead of locking the entire bus for semaphore access, the system uses a dedicated timer and mailbox mechanism that operates independently, allowing other processors to continue normal operations without bus contention. This reduces the scope of locking from bus-level to resource-level.

Inventive Principle:
Principle #2Taking out (Extraction)

3Loss of time

If a timer issues warning signals in advance, then resource preparation time is reduced, but system complexity increases due to additional timing mechanisms

Engineering Contradiction:
Improveresource preparation timeVSAvoidsystem complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The timer component serves multiple functions: it acts as a delay mechanism for resource allocation, a notification system for warning signals, and a synchronization coordinator between processors. The mailbox structure also serves dual purposes as both a communication channel and a status register. This multi-functionality reduces the need for separate dedicated components for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8099731B2System having minimum latency using timed mailbox to issue signal in advance to notify processor of the availability of the shared resources
Publication Date: 2012.01.17 IND TECH RES INST
  • US8099731B2 patent drawing
  • US8099731B2 patent drawing
  • US8099731B2 patent drawing

AI summary

The present invention provides an apparatus and method that increases the utilization by processors on shared resources. It provides the minimum latency in a multiprocessor system during usage right exchange between multi-processors on a shared resource. The apparatus provides a timed mailbox including a timer. The timed mailbox is at least associated with a first processor and a second processor. The second processor starts to utilize a shared resource to perform a task. According to a predetermined clock cycle number, the timed mailbox issues a signal in advance to notify the first processor of the availability of the shared resource to be utilized by the first processor.