Timed Multiplex Sensing for Memory Cell State Detection
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Solution Overview
Problem
Semiconductor memory technologies face increased variability in memory cell I-V characteristics and noise during sensing, leading to reduced sensing windows, which necessitate more precise and area-intensive detection circuitry, increasing die size and manufacturing costs, and longer sensing times.
Innovation Solution
The implementation of time multiplexing in detection circuitry allows for efficient detection of multiple memory cell states using shared detection circuitry, reducing the area and time required for sensing by optimizing sensing times based on previous read errors and ECC data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If detection circuitry area is increased to improve sensing precision, then measurement precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements time-multiplexed sensing where the detection circuit alternates between sensing different memory cells in periodic time slots. The sensing operation is divided into multiple phases where each phase detects a specific memory cell, allowing sequential measurement of multiple cells using a single detection circuit, thereby reducing the required circuit area while maintaining sensing precision
Solution Approach 2:
The patent adjusts sensing parameters dynamically based on detected error patterns. When read errors are detected, the system modifies sensing time durations, voltage levels, or current thresholds to optimize detection accuracy for problematic memory cells, allowing precise sensing without requiring additional hardware resources
2Measurement precision
If sensing time is increased to improve detection accuracy, then measurement precision is improved, but productivity decreases
Solution Approach 1:
The sensing process is organized into periodic time-multiplexed slots where each memory cell is sensed for an optimized duration. By alternating between multiple sensing operations in rapid succession with precisely controlled time slots, the system achieves high detection accuracy for each cell while maintaining overall high throughput and memory array productivity
Solution Approach 2:
The system uses detected error information to automatically adjust subsequent sensing parameters without external intervention. When read errors occur, the controller automatically modifies sensing times or voltages for affected cells, enabling adaptive optimization that improves accuracy without requiring additional time or manual calibration
3Reliability
If more detection circuitry is added to reduce read errors, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where detected read errors are fed back to the control logic, which then adjusts sensing parameters for subsequent operations. This closed-loop system uses error information to dynamically optimize sensing conditions, improving reliability by targeting problematic cells with enhanced detection parameters without requiring additional detection hardware
Solution Approach 2:
The single detection circuit is designed to perform multiple functions by time-multiplexing its operation across different memory cells and sensing conditions. The same circuit handles both normal sensing and error-corrected sensing, and can adapt its parameters based on the specific cell being sensed, eliminating the need for redundant specialized circuitry
Data Source
AI summary
Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.