Timed Ports for Processor Thread Scheduling
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Solution Overview
Problem
Processor designers face challenges in efficiently handling multiple external devices due to the limitations of existing interrupt handling and polling methods, which are either slow or energy-inefficient, and struggle to achieve the configurability and performance of Field Programmable Gate Arrays (FPGAs) at the cost and power levels of Application Specific Integrated Circuits (ASICs).
Innovation Solution
A processor with timed ports and a thread scheduler that uses a current time value to trigger data transfers and ready signals, allowing precise control over thread execution based on the timing of input/output operations, thereby improving reaction times and energy efficiency compared to traditional interrupt handling and polling methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If interrupt handling is used for external device communication, then the processor can respond to external events, but the reaction time is slow and energy consumption is high
Solution Approach 1:
The patent applies preliminary action by having the interface controller pre-configured with timing information and ready signals before actual data transfer is needed. The thread scheduler uses pre-established timing relationships to schedule threads without waiting for interrupts, enabling faster response while reducing energy consumption by avoiding continuous polling and interrupt handling overhead.
Solution Approach 2:
The patent introduces a timing mechanism as an intermediary between the interface controller and thread scheduler. This timing intermediary uses timed ports with trigger time values and ready signals to coordinate data transfers, eliminating the need for slow interrupt-based coordination and enabling direct, fast scheduling based on predetermined timing relationships.
2Reliability
If polling is used to check device readiness, then the processor can continuously monitor external devices, but energy consumption increases and response time is delayed
Solution Approach 1:
The interface controller pre-establishes timing information and ready signals before data transfer is needed. This preliminary configuration eliminates the need for continuous polling, as the thread scheduler can directly use the pre-configured timing relationships and ready signals to schedule threads, achieving reliable monitoring with minimal energy consumption.
3Adaptability or versatility
If FPGA devices are used for interface controllers, then configurability is achieved, but cost, power consumption, and speed decrease
Solution Approach 1:
The patent applies dynamics by implementing configurable interface controllers that can adapt their timing behavior dynamically. The interface controllers can be configured with different timing relationships, trigger time values, and ready signal characteristics, allowing the same hardware to serve multiple applications without requiring expensive FPGA devices, thus reducing power consumption while maintaining configurability.
4Use of energy by moving object
If ASIC devices are used for interface controllers, then cost and power consumption are reduced, but configurability is lost
Solution Approach 1:
The patent implements dynamic configurability in ASIC-like interface controllers through software-configurable timing parameters. The interface controllers can be programmed with different timing relationships, trigger time values, and ready signal characteristics, allowing the same low-power ASIC hardware to adapt to different applications, thus achieving both low power consumption and configurability.
Data Source
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Figure 2
Figure 2A
AI summary
A processor has an interface portion and an interior environment. The interface portion comprises: at least one port arranged to receive a current time value; a first register associated with the port and arranged to store a trigger time value; and comparison logic configured to detect whether the current time value matches the trigger time value and, provided that said match is detected, to transfer data between the port and an external environment and alter a ready signal to indicate the transfer. The internal environment comprises: an execution unit for transferring data between the at least one port and the internal environment; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions. The scheduling includes scheduling one or more of said thread for execution in dependence on the ready signal.