Timeline Dependency Graph for Dataflow Timing
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Solution Overview
Problem
Determining optimal timing constraints for data flow models in complex computer-based systems is challenging due to the complexity of heterogeneous hardware platforms and the need for intuitive mapping of applications across processing elements, which is not feasible through exhaustive exploration.
Innovation Solution
A method is introduced to determine timing constraints by creating a timeline dependency graph (TDG) based on node information, coupling between dataflow nodes, and timing information, allowing for automated mapping of program functions to distributed heterogeneous hardware platforms, considering constraints like bandwidth and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If exhaustive exploration is used to find optimal mapping, then mapping quality may be improved, but computational complexity and time consumption become infeasible
Solution Approach 1:
The patent segments the complex mapping problem into two distinct phases: (1) generating an initial mapping using a simplified evaluation function, and (2) performing localized optimization through swap operations. This segmentation avoids exhaustive exploration while still achieving high-quality mappings by focusing computational effort on promising candidates rather than evaluating all possible mappings.
Solution Approach 2:
The patent performs preliminary action by generating an initial mapping using a simplified evaluation function before applying optimization. This preliminary mapping serves as a starting point that captures the most important constraints and objectives, allowing subsequent optimization to refine the solution without needing to explore the entire solution space from scratch.
2Adaptability or versatility
If more hardware elements are integrated into the system, then system capability is improved, but system complexity increases
Solution Approach 1:
The patent implements a universal mapping framework that can handle heterogeneous hardware platforms (FPGAs, CPUs, GPUs, ASICs) using a unified evaluation function and optimization approach. The framework evaluates mappings based on multiple criteria (area, timing, bandwidth, power) simultaneously, allowing the same system to adapt to diverse hardware configurations without requiring platform-specific optimization algorithms.
Solution Approach 2:
The patent manages hardware complexity by dynamically adjusting evaluation parameters and weights based on the specific platform configuration and application requirements. The system can change the relative importance of different constraints (area vs. timing vs. bandwidth) to optimize mappings for different heterogeneous platform compositions, making the system adaptable without proportionally increasing complexity.
3Measurement precision
If timing constraints are applied to all nodes, then timing precision is improved, but computational overhead increases
Solution Approach 1:
The patent applies local quality by differentiating timing constraint application based on node characteristics. Rather than uniformly applying strict timing constraints to all nodes, the system identifies critical nodes (particularly those with side effects representing I/O operations) and applies timing constraints selectively where they are most impactful. This localized approach maintains timing precision for critical operations while reducing computational overhead for non-critical internal computations.
Data Source
AI summary
A method for determining timing constraints in dataflow models is disclosed. The method includes receiving node information specifying a plurality of dataflow nodes, as well as coupling between various ones of the dataflow nodes. The method further comprising receiving timing information specifying timing constraints for at least some of the dataflow nodes. Based on the node information, the couplings between the nodes, and the timing information, a timeline dependency graph (TDG). The timeline dependency graph illustrates a timeline, mappings between nodes with side effects to firing times of those nodes on the timeline, and dependencies between nodes.