Transaction Timeout Detection Circuit for Master-Slave Systems
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Solution Overview
Problem
Existing systems face challenges in detecting timed-out transactions between master and slave circuits without causing system resets, which can be disruptive and result in loss of diagnostic information, especially in safety-critical applications.
Innovation Solution
A timeout circuit is introduced between the master and slave circuits to track transactions, determine if expected responses are received within a timeout period, and generate the required responses and error signals to prevent hangs, while maintaining low latency and processing overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a watchdog timer is implemented as software executing on a processor to detect function completion failures, then the system can detect timeouts, but the processor becomes overloaded and system resets are triggered which cause disruption and loss of diagnostic information
Solution Approach 1:
The timeout detection function is segmented from the main processor and implemented as a dedicated hardware watchdog timer circuit. This separates the timeout monitoring task from the main processor operations, allowing independent operation without overloading the processor while maintaining reliable timeout detection capability.
Solution Approach 2:
A dedicated hardware watchdog timer circuit acts as an intermediary between the system functions being monitored and the processor. This intermediary independently monitors function completion and triggers appropriate responses without requiring processor intervention, thus reducing processor overhead while maintaining detection reliability.
2Reliability
If a system reset is triggered when timeout is detected, then the system can recover from failed functions, but human safety may be compromised and diagnostic information is destroyed
Solution Approach 1:
The system dynamically selects the appropriate response to timeout based on the nature and severity of the failure. Instead of always triggering a system reset, the watchdog timer can generate different responses including error signals, interrupt requests, or selective resets of specific modules, allowing diagnostic information to be preserved while still achieving system recovery when necessary.
Solution Approach 2:
Instead of applying a global system reset to all system components, the watchdog timer enables localized error handling where only the specific failed function or module is reset or flagged. This preserves diagnostic information in other system components while still achieving recovery of the failed function.
3Device complexity
If the watchdog timer monitors high-level functions only to avoid overloading the processor, then processor overhead is reduced, but low-level function failures cannot be detected
Solution Approach 1:
The hardware watchdog timer circuit serves as an intermediary that can monitor both high-level system functions and low-level operational parameters simultaneously. This dedicated hardware monitor handles the detailed monitoring of low-level functions without involving the processor, while still providing overall system-level timeout detection, thus achieving comprehensive coverage without processor overload.
Data Source
AI summary
The disclosure describes a circuit arrangement that includes a master circuit and a slave circuit. The master circuit generates transactions, and the slave circuit generates responses to the transactions from the master circuit. A first circuit is coupled between the master circuit and the slave circuit. The first circuit determines for each transaction from the master circuit whether the slave circuit generates an expected number of responses within a timeout period. For each transaction for which the slave circuit does not generate the expected number of responses within the timeout period, the first circuit generates and transmits the expected number of responses to the master circuit.