Timer Channel Periodic Servicing via Single Register
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Solution Overview
Problem
Existing programmable timers require multiple registers and microprocessor intervention, leading to increased hardware resource usage, latency, and high design costs, especially in custom control systems with multiple timers.
Innovation Solution
A timer system utilizing a single register with shared time base counter and storing control information in RAM, allowing automatic updates and interrupt generation, enabling efficient periodic channel servicing without microprocessor assistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple registers (master and slave) are used in each timer channel, then the timer can perform operations with minimal latency and precise control, but the hardware resource consumption increases significantly
Solution Approach 1:
The patent merges the master register and slave register functions into a single register that can be directly loaded with timer values. This eliminates the need for separate master-slave register pairs while maintaining the ability to perform precise timer operations and output compare functions.
Solution Approach 2:
The single register in each timer channel is designed to serve multiple functions: it can store timer values, receive direct loads from memory, and perform output compare operations. This multi-functional design replaces what would traditionally require separate dedicated registers for each function.
2Adaptability or versatility
If all channel service operations are performed through microprocessor/software instructions, then flexible control and programming capability are achieved, but system resources are consumed and latency increases
Solution Approach 1:
The timer channels are designed to service themselves through hardware logic that automatically loads values from memory into the single register without requiring microprocessor intervention. This self-service capability eliminates software-based timing delays while maintaining programming flexibility through memory-loaded configurations.
Solution Approach 2:
Memory serves as an intermediary between the microprocessor and the timer channel register. The microprocessor loads configuration data into memory, and the timer channel automatically reads from memory without direct processor involvement during operation, thereby reducing latency while preserving programming flexibility.
3Adaptability or versatility
If a microprocessor is used to service timer channels, then flexible control and programming capability are improved, but the cost of design and system resources increase
Solution Approach 1:
The patent extracts the timer channel servicing function from the microprocessor and implements it through dedicated hardware logic. This separation removes the microprocessor's burden of timing operations while maintaining control flexibility through hardware-based mechanisms that load values from memory automatically.
4Speed
If dedicated circuitry with master and slave registers is used, then pulse generation with minimal latency is achieved, but the hardware resources consumed are significant
Solution Approach 1:
The patent combines the functions of master and slave registers into a single register that can be directly loaded with timer values. This merging maintains the ability to generate pulses with minimal latency while reducing the hardware resources required from multiple registers to just one per channel.
Data Source
AI summary
A system and method are provided for periodically servicing a channel in a timer used for controlling events. The method services a channel in a fixed periodic cycle, and reads a first control word loaded in the channel to determine a timer operation. Then, a first data word in the channel is managed in response to the determined operation. In one aspect, a clock signal is supplied with a fixed period. Then, servicing the channel in a fixed periodic cycle includes: establishing a cycle having a first number of clock signals; and, servicing the channel for a second number of clock signals each cycle. If the timer includes a plurality of channels, then each channel is serially serviced in a single cycle.