Variable-Increment Timer Circuit for Low-Latency Frequency Adjustment
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Solution Overview
Problem
Existing timer circuits in closed-loop control circuits face delays due to fixed period values, which degrade dynamic performance by requiring changes to take effect only at the start of a new count cycle, leading to increased latency and potential corruption of switching periods.
Innovation Solution
A timer circuit with a variable increment register allows for mid-period adjustments of the count period, eliminating the need to wait for the next counting period and reducing latency by changing the increment value during the count cycle, thereby improving dynamic performance and enabling over sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the period register is updated immediately during a count cycle, then the frequency adjustment takes effect immediately improving dynamic performance, but it may generate corrupt periods and damage the power circuit
Solution Approach 1:
The patent implements dynamic period adjustment by allowing the period register to be updated during the count cycle rather than only at the start of a new cycle. The system dynamically determines whether to apply the new period value based on the current counter state, enabling flexible frequency adjustment while preventing corrupt periods through conditional logic that checks if the counter has already passed the new period value before applying the update.
Solution Approach 2:
The patent changes the parameter of period register update timing from fixed (only at count cycle start) to variable (conditional during count cycle). By monitoring the counter value and comparing it with the new period value, the system intelligently determines when to apply the period change, transforming a rigid parameter update mechanism into a flexible one that adapts to the current counting state to prevent corruption while enabling immediate frequency adjustment.
2Reliability
If the period register update waits for the next count cycle start, then corrupt periods are avoided ensuring circuit safety, but latency increases degrading dynamic performance
Solution Approach 1:
The patent transforms the fixed parameter update timing into a variable one by introducing conditional logic that evaluates the current counter state. Instead of always waiting for the next count cycle or always updating immediately, the system dynamically adjusts the update timing based on whether the counter has already reached the new period value, thereby eliminating unnecessary delays while preventing corrupt periods.
Solution Approach 2:
The patent performs preliminary checking of the counter value against the new period value before applying the period update. This preliminary action allows the system to determine in advance whether the update can be safely applied immediately or must wait for the next count cycle, thus avoiding the latency of unconditional waiting while preventing corrupt period generation.
3Device complexity
If a fixed counter increment of one is used, then the timer circuit operation is simple and reliable, but the frequency adjustment resolution is limited reducing control precision
Solution Approach 1:
The patent segments the frequency adjustment function into two independent parts: the counter increment mechanism (which remains simple with increment of one) and the period register update timing (which provides fine-grained control). By separating these functions, the system maintains simple counter operation while achieving high frequency adjustment resolution through intelligent timing control of the period updates.
Data Source
AI summary
A timer circuit is configured for providing adjustable frequency timing in a closed-loop control circuit. The timer circuit includes a period register, a counter, and a comparator. The period register is configured to hold a period value. The comparator is configured to determine when the counter reaches the period value. The timer circuit is configured to adjust the frequency by adjusting an increment controlling the counter.