Timer Circuit Interrupts for Power Management in Data Processing
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Solution Overview
Problem
Conventional data processing systems face inefficiencies in power management, particularly in switching off subsystems based on inactivity, as they do not account for scheduled events in the instruction queue, leading to potential delays and increased power consumption.
Innovation Solution
A data processing system utilizing a microprocessor, interrupt controller, and timer circuit to manage power by employing two types of interrupt signals – a fast interrupt signal for time-related events and a normal interrupt signal, allowing for precise timing and power management of subsystems like GPUs and digital signal processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional timer-based power management is used to turn off subsystems after inactivity, then power consumption is reduced, but scheduled events in the instruction queue are not accounted for causing delays and potential system failures
Solution Approach 1:
The system performs preliminary actions by saving the state of subsystems before turning them off, and by pre-scheduling wake-up events in the instruction queue. This ensures that when a scheduled event occurs, the subsystem can be reliably activated without loss of data or state, resolving the contradiction between power savings and reliable event execution
Solution Approach 2:
The system uses feedback mechanisms by monitoring the instruction queue for scheduled events and adjusting power management decisions accordingly. The timer is configured to wake up the system at specific times based on scheduled events, ensuring that power management actions do not conflict with required system operations
2Loss of energy
If the system switches to lower voltage and frequency operating points to reduce power consumption, then energy usage decreases, but processing speed and responsiveness are reduced
Solution Approach 1:
The system dynamically adjusts operating points based on real-time requirements. By using a fast interrupt mechanism, the system can quickly transition from low-power states to high-performance states when scheduled events require processing, and then return to low-power states afterward. This dynamic adjustment resolves the contradiction between energy savings and processing speed
Solution Approach 2:
The system employs periodic action by switching between low-power and high-performance modes based on scheduled events. The timer creates periodic wake-up intervals that allow the system to operate at low power consumption most of the time, while briefly activating at higher speeds when events require processing
3Duration of action of moving object
If subsystems are turned off completely to maximize power savings, then battery life is extended, but the system cannot respond to scheduled events that require those subsystems
Solution Approach 1:
The system performs preliminary actions by pre-configuring the timer with wake-up values based on scheduled events before entering low-power states. This ensures that subsystems are activated in advance of their actual need, allowing maximum power savings while maintaining event processing capability
Solution Approach 2:
The timer and instruction queue serve as intermediaries between the power management system and the subsystems. They coordinate wake-up events and ensure that subsystems are activated only when necessary, resolving the contradiction between extending battery life and maintaining productivity
Data Source
AI summary
Data processing systems with interrupts and methods for operating such data processing systems and machine readable media for causing such methods and containing executable program instructions. In one embodiment, an exemplary data processing system includes a processing system, an interrupt controller coupled to the processing system and a timer circuit which is coupled to the interrupt controller. The interrupt controller is configured to provide a first interrupt signal and a second interrupt signal to the processing system. The processing system is configured to maintain a data structure (such as, e.g., a list) of time-related events for a plurality of processes, and the processing system is configured to calise the entry of a value, representing a period of time, into the timer circuit. The timer circuit is configured to cause an assertion of the first interrupt signal in response to an expiration of the time period.