Selectable Timer Unit Circuit for Versatile PWM Output Modes
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Solution Overview
Problem
The development of microcontrollers with timer unit circuits is hindered by high costs due to the need for dedicated products for specific control applications, such as motor control, limiting versatility and increasing costs.
Innovation Solution
A timer unit circuit with a first and second counter circuit, and a selection circuit that allows for flexible operation modes, including normal-phase and reversed-phase PWM waveforms, and single-phase and two-phase output modes, enabling versatile control configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated timer unit circuit is designed for specific control applications (e.g., motor control), then the control performance and reliability are improved, but the development costs increase and versatility decreases
Solution Approach 1:
The timer unit circuit is designed with multiple counter circuits (first counter circuit with first and second counters, second counter circuit with third and fourth counters) that can be selectively activated through selection circuits. This allows a single timer unit to perform multiple functions including PWM generation, dead-time control, and various timing operations, replacing the need for multiple dedicated timer circuits for different control applications.
Solution Approach 2:
The timer unit circuit incorporates selection circuits that dynamically configure the operational mode of counter circuits based on control signals. The selection circuits enable or disable specific counter circuits and configure their operational modes (e.g., PWM generation mode, dead-time control mode), allowing the circuit to adapt its functionality in real-time without physical reconfiguration.
2Reliability
If a dedicated timer unit circuit is designed for specific control applications, then the control functionality is improved, but the development costs increase
Solution Approach 1:
The timer unit circuit integrates multiple counter circuits and selection circuits into a single unified structure that can perform various control functions. By sharing common resources (clock signals, control circuits, output circuits) among multiple counter circuits, the design reduces the total component count and development costs compared to implementing separate dedicated timer circuits for each function.
Solution Approach 2:
The patent combines multiple counter circuits (first counter, second counter, third counter, fourth counter) and their associated control logic into a single timer unit circuit. The selection circuits merge the control paths, allowing a single control signal to configure multiple counter circuits for different functions, thereby reducing overall circuit complexity and development costs.
3Adaptability or versatility
If multiple dedicated timer circuits are used for different control functions, then the adaptability to various control applications is improved, but the device complexity increases
Solution Approach 1:
The timer unit circuit achieves high adaptability through a unified multi-functional architecture. The first and second counter circuits can be configured for PWM generation, dead-time control, and timing functions, while the third and fourth counter circuits provide additional timing capabilities. The selection circuits enable dynamic configuration, allowing the same hardware to adapt to various control applications without increasing physical circuit complexity.
Solution Approach 2:
The timer unit circuit is segmented into modular counter circuits (first, second, third, and fourth counters) that can be independently configured and controlled. Each counter circuit can operate autonomously or in combination with others, allowing flexible configuration for different control functions while maintaining manageable circuit complexity through modular design.
Data Source
AI summary
A timer unit includes a first selector that receives a fixed value and a first enable signal, a second selector that receives the fixed value and a count cycle signal, a third selector that receives an output of the second selector, the count cycle signal, and a second enable signal, a first counter circuit that starts counting in response to an output of the first selector, and that generates the count cycle signal and a first counter circuit output signal indicating that a count value approaches a predetermined value, a second counter circuit that starts counting in response to an output of the third selector, and that generates a second counter circuit output signal, a first output signal generator that receives the first counter circuit output signal and the second counter circuit output signal to generate a first output signal, and a second output signal generator.