Timer Circuit Test Mode Segmentation for Production Efficiency

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Solution Overview

Problem

The time-consuming production testing of integrated circuit timers, which involves substantial delays for power-up and power-down cycles, results in significant time and cost expenditures due to the need to evaluate both portions of the timer circuit during each phase, making the process inefficient and costly.

Innovation Solution

A timer circuit with a normal mode and a test mode, where only the first portion is tested during the power-up phase and only the second portion during the power-down phase, allowing for the entire timer circuit to be tested in a single power-up/power-down cycle, thereby reducing testing time and expenses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If both portions of the timer circuit are tested in each phase (power-up and power-down), then comprehensive testing coverage is achieved, but testing time and cost increase substantially

Engineering Contradiction:

Improvetesting coverageVSAvoidtesting time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The timer circuit is divided into two distinct portions: a first timer circuit portion and a second timer circuit portion. Each portion is tested during a different phase of the power cycle - the first portion during power-up and the second portion during power-down. This segmentation allows comprehensive testing coverage while reducing the time required in each individual phase, as only one portion needs to be tested at a time rather than both portions simultaneously.

Inventive Principle:

Principle #1Segmentation

2Reliability

If the full timer delay is implemented during testing, then normal operation performance is accurately evaluated, but production test time increases significantly

Engineering Contradiction:

Improveperformance evaluation accuracyVSAvoidproduction test throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The timer circuit operates in different modes depending on the phase: during normal operation, the full timer delay is implemented for proper performance; during production testing, the circuit dynamically switches to a test mode where only the necessary portion is activated. This dynamic operation allows accurate performance evaluation when needed while maintaining high production throughput during manufacturing testing.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The test mode is configured in advance to bypass the full timer delay sequence by directly testing individual portions during specific phases. This preliminary configuration allows the testing system to skip unnecessary waiting periods while still accurately evaluating the timer's functionality, thereby improving production test throughput without sacrificing evaluation accuracy.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If comprehensive timer circuit testing is performed in a single phase, then complete functionality is verified, but time expenditure for each phase increases

Engineering Contradiction:

Improvefunctionality verificationVSAvoidphase duration

Core Design Contradiction:

ReliabilityVSDuration of action of moving object

Solution Approach 1:

The testing process is segmented across two phases: power-up phase tests the first timer circuit portion, and power-down phase tests the second timer circuit portion. This segmentation distributes the total testing workload across both phases, reducing the duration required in each individual phase while maintaining complete functionality verification through the combined testing coverage of both portions.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS7298223B1Methods and systems for electronic component test time improvement

Publication Date: 2007.11.20 NAT SEMICON CORP

AI summary

A timer circuit that has a normal mode and a test mode is disclosed. The test mode includes a power-up phase and a power-down phase. The timer circuit includes an oscillator and a first timer circuit portion coupled to the oscillator. The first timer circuit portion includes an input and an output. An output signal that confirms either the satisfactory or unsatisfactory operation of the first timer circuit portion is taken from the output associated with the first timer circuit portion in the power-up phase. The timer circuit further includes a second timer circuit portion coupled to the first timer circuit portion and the oscillator. The second timer circuit portion also includes an input and an output. An output signal that confirms either the satisfactory or unsatisfactory operation of the second timer circuit portion is taken from the output associated with the second timer circuit portion in the power-down phase.