Timer Clock Pulse Width Adjustment for Access Timing Trade-offs
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Solution Overview
Problem
Existing timers with asynchronous counters face challenges in completing timing operations quickly due to overlapping timing and access signals, leading to potential errors in timing data generation when the clock pulse signal width is shortened to prioritize access.
Innovation Solution
A timer design that adjusts the clock pulse signal width based on the presence or absence of an access signal, using a first pulse width when access is possible and a second, longer pulse width when access is not, determined by the power supply voltage, ensuring accurate timing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the pulse width of the clock pulse signal is shortened to enable fast access from external devices, then access speed is improved, but the timing counter may fail to complete the timing operation and generate wrong timing data
Solution Approach 1:
The clock pulse signal width is made dynamically adjustable based on operational mode. The control circuit switches between a first clock pulse signal (narrow width) for fast access mode and a second clock pulse signal (wide width) for accurate timing mode, allowing the system to adapt its timing characteristics to current operational requirements
Solution Approach 2:
The pulse width parameter of the clock signal is changed based on the operational state. When fast access is required, a narrow pulse width is used; when timing accuracy is critical, a wider pulse width is applied. This parameter adjustment resolves the contradiction by optimizing the clock signal characteristics for different operational contexts
2Reliability
If the pulse width of the clock pulse signal is increased to ensure complete timing operation, then timing operation reliability is improved, but access speed from external devices is reduced
Solution Approach 1:
The system dynamically selects between two clock pulse signal widths based on the current operational mode. The control circuit enables switching between narrow pulses (for fast access) and wide pulses (for reliable timing), allowing the timing counter to complete operations accurately when needed while maintaining fast access capability when timing criticality is reduced
Solution Approach 2:
The clock pulse signal width parameter is adjusted according to operational requirements. The control circuit selects appropriate pulse widths (first width for fast access, second width for accurate timing) based on system state, resolving the trade-off between access speed and timing reliability
3Measurement precision
If the timing operation is prioritized over access signal processing, then timing data accuracy is improved, but access signal response is delayed
Solution Approach 1:
The control circuit dynamically adjusts the clock pulse signal characteristics based on whether fast access mode is active. When fast access is required, the narrow clock pulses enable quicker response to access signals while maintaining sufficient timing accuracy through the adjusted pulse width
Solution Approach 2:
The clock pulse signal parameters are changed based on operational mode to balance timing accuracy and access response. The control circuit selects appropriate pulse widths that maintain timing data accuracy while enabling fast access signal processing when needed
Data Source
AI summary
A timer includes a timing counter configured to generate a timing datum, a clock pulse signal generation circuit configured to generate a clock pulse signal used to operate the timing counter, and an interface circuit configured to receive an access signal, wherein the timing counter is an asynchronous counter, and the clock pulse signal generation circuit generates the clock pulse signal having a first pulse width when there is a possibility that the interface circuit receives the access signal, and generates the clock pulse signal having a second pulse width longer than the first pulse width when there is no possibility that the interface circuit receives the access signal.