Timer Circuit Error Checking for Reliable System Time Sync
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Solution Overview
Problem
Current processing systems in automotive applications face challenges in generating and synchronizing a reliable time reference across multiple processing units, which is crucial for synchronized operations and safety, but existing solutions are inadequate in ensuring availability, correctness, and integrity of the time-base value.
Innovation Solution
A processing system with a timer circuit configured to generate a system time signal and transmit it to a processing circuit via a parallel time bus, using error detection and correction mechanisms to ensure accuracy and reliability, along with watchdog timers and analog clock monitors to detect malfunctions and maintain correct time evolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a timer circuit generates and transmits system time signal to processing circuits, then synchronized operations across processing units are enabled, but the reliability and integrity of the time reference may be compromised due to potential errors in generation and transmission
Solution Approach 1:
The patent implements error detection circuits in both the timer circuit and processing circuits that continuously monitor the system time signal. When errors are detected in the generated or transmitted time signal, the system can identify and correct these errors through the feedback mechanism provided by the error detection circuits, thereby maintaining reliability without requiring overly complex redundant systems
Solution Approach 2:
The patent introduces error detection circuits as intermediary components between the timer circuit and processing circuits. These intermediary circuits act as mediators that detect and flag errors in the time signal transmission, allowing the system to maintain reliable operation by identifying issues before they compromise the time reference integrity
2Measurement precision
If error detection and correction mechanisms are implemented in the time signal transmission, then accuracy and reliability of time reference are ensured, but the device complexity increases
Solution Approach 1:
The patent implements error detection circuits that create copies of the system time signal for verification purposes. By generating and comparing copies of the time signal through error detection circuits, the system can verify accuracy without requiring completely redundant time generation systems, thus maintaining precision while controlling complexity
Solution Approach 2:
The patent employs error detection and correction mechanisms that monitor and verify parameters of the system time signal (such as bit integrity and signal characteristics). By changing and verifying these parameters through error detection circuits, the system ensures time signal accuracy without requiring overly complex verification systems
3Reliability
If watchdog timers and analog clock monitors are added to detect malfunctions, then safety and reliability are enhanced, but the device complexity and power consumption increase
Solution Approach 1:
The patent implements watchdog timers and analog clock monitors that operate periodically to detect malfunctions in the time reference system. By using periodic monitoring instead of continuous monitoring, the system enhances safety and reliability while reducing power consumption compared to continuously active monitoring systems
Solution Approach 2:
The patent employs watchdog timers and monitoring circuits that can detect and respond to malfunctions without requiring expensive, highly complex redundant time reference systems. These monitoring components provide adequate safety enhancement at lower power consumption and cost, accepting limited lifespan or operational duration when needed
Data Source
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AI summary
A processing system (10a) is described. The processing system (10a) comprises a timer circuit (122) and a processing circuit (110). The timer circuit (122) generates, in response to a clock signal (CLK), a system time signal (GST) comprising a plurality of bits indicative of a time tick-count. The processing circuit (110) receives the system time signal (GST), detects (1102) whether the system time signal (GST) reaches or exceeds a given reference value, and starts execution of a given processing operation in response to the detection. Specifically, the timer circuit (122) has associated an error code calculation circuit (1230) configured to compute a first set of error detection bits (EDB) as a function of the bits of the system time signal (GST). The processing circuit (110) has associated an error detection circuit (1112). The error detection circuit (1112) computes a second set of error detection bits as a function of the bits of said system time signal (GST) received, compares the first set of error detection bits (EDB) with the second set of error detection bits, and generates an error signal (ERR2) in response to the comparison.