IoT Time Synchronization via Timer-to-I/O Transport Delay Calibration
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Solution Overview
Problem
The precision of clock synchronization in Time Sensitive Networking (TSN) is limited by the discrepancy between software and network clocks, leading to increased latency and jitter in time-sensitive applications, which affects network performance in IoT devices.
Innovation Solution
IoT devices incorporate an additional serial signal wire between the central timer and I/O devices to determine and correct transport delays, enabling precise internal time synchronization by calculating transport delay values and adjusting timestamps accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If software repeatedly samples internal time and network time on NIC, then clock synchronization is achieved, but precision is limited by minimum read latency between processor and network time
Solution Approach 1:
The patent introduces a dedicated time-stamping circuit as an intermediary component between the network interface controller and the processor. This circuit independently captures timestamps for network packets without requiring processor intervention, thereby eliminating the read latency bottleneck while maintaining synchronization precision. The intermediary circuit acts as a buffer that decouples the time-critical timestamping function from the slower processor sampling operations.
2Measurement precision
If TSN controllers are integrated into embedded designs, then network clock synchronization capability is improved, but discrepancy between software clock and network clock increases
Solution Approach 1:
The patent replaces the software-based clock sampling mechanism with a hardware-based time-stamping circuit. This substitution eliminates the fundamental discrepancy between software clock and network clock by capturing timestamps in hardware at the exact moment packets are received, bypassing the software processing delays and inconsistencies that cause clock divergence.
3Measurement precision
If processor reads timestamp counter instructions are used, then software clock time is obtained, but precision is limited by processor read latency
Solution Approach 1:
The dedicated time-stamping circuit serves as an intermediary that captures timestamps independently of processor operations. The circuit receives network packets and immediately records precise timestamps in hardware registers, eliminating the need for processor to read timestamp counter instructions. This intermediary mechanism decouples timestamp acquisition from processor latency, achieving nanosecond-level precision without processor intervention.
Data Source
AI summary
Technologies for managing internal time synchronization include an internet-of-things (IoT) device configured to determine a transport delay value as a function of a transmit path delay corresponding to a first message transmitted from an I/O device of the IoT device to a central timer of the IoT device and a receive path delay corresponding to a second message transmitted from the central timer to the I/O device. The IoT device is further configured to update, in response to having received a broadcast message from the central timer subsequent to having determined the transport delay value, a timestamp value of the received broadcast message as a function of the transport delay value. Other embodiments are described herein.