Hardware Timer Manager with Segmented Precision Checking

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Solution Overview

Problem

Existing timer managers are costly and inefficient in managing a large number of timers with varying precision levels and expiration periods, leading to resource wastage and increased design complexity.

Innovation Solution

A timer manager that supports multiple precision levels by grouping timers and checking them at different frequencies, allowing for efficient management of timer entries with automatic expiration event scheduling and timestamp synchronization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a timer manager tracks a large number of timers with high precision, then measurement precision is improved, but device complexity and cost increase

Engineering Contradiction:
Improvetimer precisionVSAvoidtimer manager complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The timer manager divides timer entries into multiple groups (first group, second group, etc.), where each group can be checked at different frequencies. This segmentation allows high-precision timing for critical timers while using lower precision for less critical ones, reducing overall system complexity and resource requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different groups of timer entries are assigned different precision levels and checking frequencies based on their specific requirements. The first group of timer entries is checked more frequently than the second group, providing locally optimized precision for different timer categories rather than uniform high precision across all timers.

Inventive Principle:
Principle #3Local quality

2Reliability

If the timer manager checks all timer entries frequently, then reliability of timer expiration detection is improved, but productivity of other system operations decreases

Engineering Contradiction:
Improvetimer expiration detectionVSAvoidsystem operation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The timer checking process is segmented into multiple groups with different checking frequencies. The hardware logic checks the first group of timer entries more frequently than the second group, ensuring reliable detection for critical timers while reducing overall checking overhead and improving system productivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different groups of timer entries are checked at different periodic intervals. The first group is checked more frequently than the second group, allowing the system to balance reliability of timer expiration detection with productivity of other operations by adjusting the periodicity of checks for different timer categories.

Inventive Principle:
Principle #19Periodic action

3Adaptability or versatility

If the timer manager supports multiple precision levels, then adaptability is improved, but device complexity increases

Engineering Contradiction:
Improveprecision level supportVSAvoidtimer manager structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The timer manager structure is segmented into multiple groups of timer entries, where each group can be configured with different precision levels. This segmentation provides adaptability for supporting multiple precision levels while keeping the overall structure manageable through systematic organization of timer groups with varying characteristics.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250258516A1Hardware Timer Manager Supporting Multiple Precision Levels
Publication Date: 2025.08.14 TEXAS INSTRUMENTS INC
  • US20250258516A1 patent drawing
  • US20250258516A1 patent drawing
  • US20250258516A1 patent drawing

AI summary

A hardware timer manager may be employed in a network accelerator. The timer manager may support multiple precision levels of timers. A timer manager may split up a total group of supported timer entries into multiple precision groups in a memory. The timer manager may check a programmed number of timer entries in a highest precision group before checking a single programmed timer entry in the next group, and repeating this checking scheme until a timer entry in a lowest precision group is checked, then repeating it from the start.