Timer Module Redundant Signal Error Detection

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Solution Overview

Problem

Existing timer modules in safety-critical applications, such as automotive control units, face challenges in efficiently and reliably detecting errors in redundant output signals without interrupting the processing unit or requiring additional synchronization steps.

Innovation Solution

Implementing an EXOR logic operation for bitwise comparison of redundant output signals, allowing for synchronous error detection and reporting, with the option to configure the comparison process and store error signals in a status register for external processing unit access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If synchronous comparison of redundant output signals is implemented using traditional methods (stop signal or FIFO memory), then error detection reliability is improved, but processing time and system complexity increase

Engineering Contradiction:
Improveerror detection reliabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-configuring the comparison module and status register before comparison is needed. The system pre-establishes the EXOR logic operation framework and status register structure, so that when redundant output signals need comparison, the infrastructure is already in place and ready for immediate operation, eliminating setup delays

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts the comparison function as a separate, dedicated comparison module that operates independently from the main processing unit. This extracted comparison module continuously monitors redundant output signals using EXOR logic without requiring the main processor to intervene or pause, thereby maintaining processing time while ensuring error detection reliability

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If traditional comparison methods with stop signals or FIFO memory are used, then error detection capability is improved, but device complexity increases

Engineering Contradiction:
Improveerror detection capabilityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces complex mechanical synchronization mechanisms (stop signals, FIFO memory units) with a simpler electronic logic solution. The EXOR logic operation in the comparison module provides automatic bitwise comparison of redundant signals without requiring mechanical intervention or complex memory management, thereby reducing device complexity while maintaining error detection capability

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The comparison module performs self-service by autonomously comparing redundant output signals using EXOR logic and automatically updating the status register with error identifiers. This self-service mechanism eliminates the need for external control signals or complex coordination with the main processing unit, simplifying the overall system architecture while ensuring reliable error detection

Inventive Principle:
Principle #25Self-service

3Productivity

If error signals are immediately cleared after detection, then processing efficiency is improved, but error tracking and diagnostics capability deteriorates

Engineering Contradiction:
Improveprocessing efficiencyVSAvoiderror tracking capability
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The status register is pre-configured with specific bit positions dedicated to storing error identifiers from comparison operations. This preliminary preparation allows error information to be immediately captured and retained in designated locations without interfering with ongoing processing, maintaining processing efficiency while preserving error tracking capability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The status register serves as an intermediary between the comparison module and the external processing unit. It temporarily holds error identifiers generated by the comparison operation, allowing the main processor to continue its work uninterrupted while error information is preserved for later retrieval and analysis, thus balancing processing efficiency with error tracking capability

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9501370B2Timer module and method for testing output signals of a timer module
Publication Date: 2016.11.22 ROBERT BOSCH GMBH
  • US9501370B2 patent drawing
  • US9501370B2 patent drawing
  • US9501370B2 patent drawing

AI summary

In a timer module having at least two output channels, the at least two output channels are configurable in such a way that they generate redundant output signals, and the generation of the redundant output signals begins synchronously. In addition, the timer module has provides a comparison of the redundant output signals by an EXOR logic operation and stores a result of the EXOR logic operation in a way that allows the result to be retained for an erroneous comparison until it is reset by an access.