Timer-Interrupt Packet Dequeuing for Low-Latency Server Networking
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Solution Overview
Problem
Existing packet transfer methods in server virtualization environments, such as the interrupt and polling models, suffer from increased delays due to contention with other interrupts or CPU usage, leading to inefficient packet processing.
Innovation Solution
A server delay control device that utilizes a timer interrupt to monitor packet arrivals and perform dequeuing operations without modifying the application layer, incorporating a packet arrival monitoring part and a packet dequeuer to manage the ring buffer and poll list, reducing the need for software interrupts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the interrupt model is used for packet transfer, then packet processing can be triggered by hardware interrupts, but delays increase due to contention with other interrupts and CPU usage
Solution Approach 1:
The patent extracts the packet dequeuing operation from the software interrupt context and performs it in the hardware interrupt context directly. By removing the software interrupt step that causes contention and delay, the system achieves lower packet transfer delay while maintaining reliable packet processing through direct hardware-triggered dequeuing.
Solution Approach 2:
The patent introduces a ring buffer as an intermediary data structure between the network device and the packet processing application. The ring buffer enables the hardware interrupt to directly access and dequeue packets without requiring software interrupt mediation, thereby reducing delay while maintaining processing reliability.
2Ease of operation
If software interrupts are used for packet processing, then packet transfer can be coordinated with CPU tasks, but CPU occupancy increases and transfer delays occur
Solution Approach 1:
The patent extracts the packet dequeuing function from software interrupt handling and implements it within the hardware interrupt context. This eliminates the need for CPU occupancy in software interrupt processing, reducing CPU occupancy time while maintaining ease of operation through direct hardware-triggered packet retrieval.
Solution Approach 2:
The hardware interrupt mechanism performs packet dequeuing autonomously without requiring CPU intervention through software interrupts. The system achieves self-service packet processing where the hardware interrupt context directly manages packet retrieval from the ring buffer, minimizing CPU occupancy while maintaining operational ease.
3Reliability
If the polling model is used to monitor packets, then packet arrival can be detected without interrupts, but CPU occupancy increases continuously
Solution Approach 1:
The patent extracts the packet monitoring function from continuous CPU polling and implements it through hardware interrupt-triggered dequeuing. By removing the continuous polling requirement, the system achieves reliable packet arrival detection without continuous CPU occupancy, as packets are detected and dequeued only when hardware interrupts occur.
Data Source
AI summary
Provided is a server delay control device for a server in which an OS having a kernel is deployed. The OS includes: a ring buffer managed by the kernel; and a poll list in which information on a net device of a hardware interrupt from an NIC is registered. The server delay control device is deployed in the server and configured to receive a timer interrupt at predetermined specified intervals and monitors a packet arrival and includes: a packet arrival monitoring part configured to check the presence or absence of a packet in the poll list upon being triggered by the timer interrupt to monitor the poll list; and a packet dequeuer configured to, when a packet has arrived, reference the packet held in the ring buffer, and perform dequeuing to remove the corresponding queue entry from the ring buffer.