Dynamic Timer Prescaler Correction for RTC Time Drift
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Solution Overview
Problem
Existing systems face challenges in accurately maintaining a consistent time base due to variations in temperature and voltage, leading to timing errors in system timers, which can cause inconsistencies in communication protocols and increase system complexity and cost.
Innovation Solution
The implementation of a dynamic error correction mechanism using clock divider circuitry, counter circuitry, comparison circuitry, and controller circuitry that adjusts the pre-scaler input to modify the frequency of the divided clock, thereby gradually correcting the system timer count to match the real-time clock count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the system timer uses a system clock for time keeping, then the system timer can operate with high speed and resolution, but timing errors occur due to variations in temperature and voltage affecting clock accuracy
Solution Approach 1:
The patent implements a feedback mechanism where the system timer continuously compares its count with the RTC count and dynamically adjusts the pre-scaler value based on the detected timing error. This closed-loop feedback system corrects timing drift caused by temperature and voltage variations, maintaining accurate time keeping without sacrificing the high-speed operation of the system timer.
Solution Approach 2:
The patent changes the pre-scaler parameter dynamically to compensate for timing errors. By adjusting the pre-scaler value based on the difference between system timer count and RTC count, the system adapts to environmental variations (temperature and voltage) that affect clock accuracy, thereby maintaining reliable time base consistency.
2Use of energy by moving object
If the system timer count is reset when the system power domain is powered down, then power consumption is reduced, but timing continuity is broken and requires correction mechanisms
Solution Approach 1:
The patent performs preliminary action by saving the RTC count before powering down the system timer and restoring it after power-up. This preliminary preparation ensures that when the system timer resumes operation, it can continue from the correct time point, maintaining time base continuity without requiring complex correction mechanisms during operation.
Solution Approach 2:
The RTC count serves as an intermediary that bridges the gap between power-down and power-up states. By using the RTC count as a reference and comparison value, the system timer can detect and correct timing discontinuities caused by power cycling, maintaining stability without compromising power savings.
3Measurement precision
If dynamic error correction is implemented by comparing system timer count with RTC count, then timing accuracy is improved, but device complexity increases due to additional circuitry
Solution Approach 1:
The patent implements multi-functionality by using the RTC count for multiple purposes: it serves as a reference for error detection, a comparison value for timing accuracy, and a restoration point for power-cycle recovery. This universal use of the RTC count reduces the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity while maintaining high time keeping accuracy.
4Reliability
If the pre-scaler value is modified dynamically to correct timing errors, then time base consistency is maintained, but control complexity increases
Solution Approach 1:
The patent applies dynamics by making the pre-scaler value adjustable and adaptive rather than fixed. The control logic dynamically modifies the pre-scaler based on real-time comparison between system timer count and RTC count, enabling the system to adapt to environmental variations and maintain time base consistency. This dynamic approach replaces complex predictive control with simple reactive adjustment.
Data Source
AI summary
An example apparatus includes clock divider circuitry configured to divide a system clock by a pre-scaler input to generate a divided clock; counter circuitry configured to increment a system count based on the divided clock; comparison circuitry configured to determine a count difference between the system count and a real-time clock count; and controller circuitry configured to modify the pre-scaler input based on a comparison of the count difference to a threshold value.