Clock Synchronization Circuit With Feedback for Timer-Sampling Drift

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Solution Overview

Problem

In cellular communication systems, especially with free-running references, there is a challenge in maintaining alignment between timer and sampling frequencies, leading to potential call drops due to phase and frequency drifts, particularly in scenarios where the sampling frequency is derived from the radio frequency and varies with the carrier frequency, requiring high hardware effort to keep frequencies identical.

Innovation Solution

A circuit arrangement that includes an analog-to-digital converter, a decimation circuit, a timer circuit, and a difference determination circuit to detect and correct phase differences between the timer and sampling frequencies, using a feedback control loop to ensure alignment and reduce errors, thereby reducing hardware complexity and compensating for non-deterministic effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If separate correction is applied to timer and sampling frequencies in a free-running system, then frequency sharing between multiple systems is enabled, but phase and frequency drift accumulate leading to call drops

Engineering Contradiction:
Improvefrequency sharing capabilityVSAvoidcall stability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the phase difference between timer signal and sampling signal is continuously measured and used to adjust the sampling frequency. This closed-loop control prevents drift accumulation while maintaining the free-running system's ability to share frequencies across multiple systems.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent introduces a phase difference measurement unit as an intermediary component that monitors the relationship between timer and sampling frequencies. This intermediary enables indirect control of sampling frequency based on timer reference, allowing separate correction while maintaining synchronization.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If sampling frequency is derived directly from radio frequency, then sampling can track carrier frequency variations, but hardware complexity increases significantly

Engineering Contradiction:
Improvefrequency tracking capabilityVSAvoidhardware effort
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent replaces direct hardware-based frequency derivation with a software/digital approach. Instead of using complex hardware circuits to track carrier frequency variations, the system uses a programmable sampling frequency controller that adjusts sampling rate based on measured phase difference, reducing hardware complexity while maintaining tracking capability.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the sampling frequency parameter dynamically based on carrier frequency variations. By allowing the sampling frequency to be adjusted as a controllable parameter rather than being fixed by hardware derivation, the system achieves frequency tracking with reduced hardware complexity.

Inventive Principle:
Principle #35Parameter changes

3Stability of the object's composition

If fixed coupling between timer and sampling frequency is used, then frequency alignment is maintained, but separate frequency corrections cannot be applied

Engineering Contradiction:
Improvefrequency alignmentVSAvoidindependent correction capability
Core Design Contradiction:
Stability of the object's compositionVSAdaptability or versatility

Solution Approach 1:

The patent segments the frequency correction process into two independent parts: timer frequency correction and sampling frequency correction. The timer operates with its own reference while the sampling frequency is corrected separately based on phase difference measurement, allowing both to be adjusted independently while maintaining their relationship through feedback control.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10356736B2Circuit arrangement for clock synchronization
Publication Date: 2019.07.16 APPLE INC
  • US10356736B2 patent drawing
  • US10356736B2 patent drawing
  • US10356736B2 patent drawing

AI summary

A circuit arrangement may include an analog-to-digital-converter (ADC) configured to convert an analog signal into a digitized signal having an ADC frequency, a decimation circuit configured to provide a first signal having a sampling frequency based on the digitized radio signal having the ADC frequency. The sampling frequency is smaller than the ADC frequency. The circuit arrangement may further include a timer circuit providing a second signal having a timer frequency and a timing control signal to control the timing of the decimation circuit, and a difference determination circuit configured to determine a phase difference between the second signal and the first signal.