Timer Tick Generation by Alternating Clock Division Ratios

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Solution Overview

Problem

Timers generating ticks at predetermined cycles using clock signals often accumulate errors, making it difficult to use these ticks directly as system ticks without complex algorithms or sophisticated hardware.

Innovation Solution

Generating a periodic timing signal with a first frequency by dividing an input clock signal, and switching it to a second frequency to inhibit error accumulation, with alternating frequency changes to maintain a zero average error between the timing signal and the desired timer frequency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a timer generates ticks by counting clock signals at a fixed division ratio, then the timer operation is simple and stable, but timing error accumulates over time

Engineering Contradiction:
Improvetiming accuracyVSAvoiderror compensation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies periodic action by alternating between two different clock signal division ratios (first and second division ratios) in a periodic manner. The timer switches between generating ticks at a first frequency and a second frequency, where the second frequency differs from the first. This periodic switching creates a compensatory effect where timing errors generated during one phase are corrected during the other phase, maintaining long-term timing accuracy without requiring complex error compensation algorithms or additional hardware components.

Inventive Principle:
Principle #19Periodic action

2Reliability

If the timer uses a single division ratio to generate ticks, then the hardware is simple, but the timing error accumulates as time passes

Engineering Contradiction:
Improvetiming accuracyVSAvoidhardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies dynamics by making the clock signal division ratio variable rather than fixed. The timer dynamically switches between a first division ratio and a second division ratio based on a switching signal. This dynamic adjustment allows the timer to adapt its operating parameters periodically, generating ticks at alternating frequencies that compensate for accumulated timing errors. The dynamic switching is implemented through simple control logic that monitors tick counts and triggers frequency switching, achieving improved timing accuracy without significant hardware complexity increase.

Inventive Principle:
Principle #15Dynamics

3Measurement precision

If the timer alternates between two frequencies to compensate error, then timing accuracy is maintained, but the control logic becomes more complex

Engineering Contradiction:
Improvetick generation precisionVSAvoidcontrol logic complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the tick generation process into distinct phases corresponding to different division ratios. A tick counter is segmented to track the number of ticks generated at the first frequency, and switching decisions are made based on segmented thresholds (first threshold and second threshold). This segmentation of the control logic into discrete, manageable states simplifies the overall control complexity while maintaining precise tick generation. Each segment operates with simple comparison logic against predefined thresholds, avoiding the need for complex continuous error calculation and compensation algorithms.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8797083B2Methods of operating timers to inhibit timing error accumulation
Publication Date: 2014.08.05 SAMSUNG ELECTRONICS CO LTD
  • US8797083B2 patent drawing
  • US8797083B2 patent drawing
  • US8797083B2 patent drawing

AI summary

Methods of operating timers include generating a periodic timing signal having a first frequency that differs from a desired timer frequency (1 KHz) by a first amount. This periodic timing signal having the first frequency can be generated by dividing a frequency of an input clock signal (e.g., 32.768 KHz) by N, where N is a positive integer greater than one. A typical value of N may be 32. The methods also include techniques to inhibit timing error accumulation by switching a frequency of the periodic timing signal from the first frequency to a second frequency that differs from the desired timer frequency by a second amount. This periodic timing signal having the second frequency can be generated by dividing the frequency of the input clock signal by M, where M is a positive integer unequal to N (e.g., M−N equals ±1).