Time-shared MAC Logic for Multi-Protocol Network Sub-Ports

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Solution Overview

Problem

Current network devices face challenges in efficiently processing information across different protocols and clock rates, leading to issues such as under-run and over-run conditions, which can result in data corruption and inefficient data transfer.

Innovation Solution

A network device with a base-port having multiple sub-ports that can operate independently at various rates, using a temporary storage device and a time-shared MAC module to process information at a unified clock rate, allowing each sub-port phased access to the logic for processing data conforming to different protocols.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a network device uses separate processing logic for each protocol and clock rate, then processing accuracy for each protocol is improved, but device complexity increases

Engineering Contradiction:
Improveprocessing accuracyVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a universal MAC module that can process multiple protocols (Ethernet, Fibre Channel, InfiniBand) through a single unified processing logic. The module uses protocol identification circuits to detect the incoming protocol type and configures itself accordingly, eliminating the need for separate dedicated processing logic for each protocol while maintaining processing accuracy through protocol-specific configuration parameters

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If the network device processes data at multiple different clock rates simultaneously, then adaptability to different protocols is improved, but data synchronization becomes difficult

Engineering Contradiction:
Improveprotocol compatibilityVSAvoiddata synchronization
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces a clock rate conversion circuit as an intermediary between the unified MAC module and the external network interfaces. This converter receives data at various input clock rates, converts it to a standardized internal clock rate for unified processing, and then converts back to the required output clock rate, ensuring synchronous data transfer and preventing under-run/over-run conditions

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system dynamically adjusts clock rate parameters based on the detected protocol type. The clock rate conversion circuit modifies its conversion ratios according to the protocol being processed, allowing the unified MAC module to handle different protocols at their respective clock rates while maintaining internal synchronization through parameter adaptation

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If the network device uses a unified MAC module for multiple sub-ports, then device complexity is reduced, but processing speed for each sub-port may decrease

Engineering Contradiction:
Improvedevice complexityVSAvoidprocessing speed
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The unified MAC module processes data from multiple sub-ports in periodic time slots, dedicating specific time periods to each sub-port. This time-division multiplexing approach allows the single MAC module to service multiple sub-ports sequentially at full speed, achieving the same throughput as dedicated modules would provide while maintaining lower device complexity

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS9046941B1System and method for sharing logic in a network device
Publication Date: 2015.06.02 MARVELL ASIA PTE LTD
  • US9046941B1 patent drawing
  • US9046941B1 patent drawing
  • US9046941B1 patent drawing

AI summary

Method and system for processing information at a network device connected to a network is provided. The method includes receiving information conforming to a first protocol at a first clock rate at a first sub-port; receiving information conforming to a second protocol at a second clock rate at a second sub-port; storing received information in a temporary storage device at the base-port; reading information out of the temporary storage device at a third clock rate; and processing the information at a MAC module that includes logic that is time-shared among the plurality of sub-ports to process information at the third rate for both the first protocol and the second protocol. The first sub-port is granted access to the logic in a first phase and the second sub-port is granted access to the logic in a second phase for processing the information.