Timeslot Arbiter for Shared Memory Bandwidth Allocation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing shared memory devices experience long and unpredictable latency when accessed by multiple central processing units (CPUs) due to traditional round-robin arbitration methods, leading to inefficient data transfer and increased power consumption.
Innovation Solution
A timeslot arbiter system that generates a clock signal and determines a sequence for selecting agents to access a shared memory unit based on their bandwidths, allowing parallel data transfer in a single clock cycle, thereby reducing latency and optimizing bandwidth usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If round-robin arbitration is used to access shared memory, then access fairness is maintained, but latency becomes long and unpredictable
Solution Approach 1:
The patent implements dynamic bandwidth allocation where the arbiter assigns different timeslots to different agents based on their bandwidth requirements. Instead of equal round-robin access, the system dynamically adjusts access patterns to match actual data transfer needs, allowing agents with higher bandwidth requirements to access memory more frequently while maintaining fairness through weighted allocation.
Solution Approach 2:
The patent changes the arbitration parameter from simple turn-based counting to bandwidth-weighted timeslot allocation. The arbiter receives bandwidth information from agents and uses this parameter to determine timeslot distribution, transforming the static round-robin approach into a dynamic bandwidth-aware scheduling mechanism that reduces latency while maintaining fairness.
2Device complexity
If traditional shared memory access methods are used, then device simplicity is maintained, but system bandwidth is reduced
Solution Approach 1:
The patent segments the memory access times into distinct timeslots allocated to different agents. By dividing the access period into multiple timeslots that can be independently allocated based on bandwidth requirements, the system enables parallel data transfer operations without requiring complex multi-port hardware, thus improving bandwidth while maintaining reasonable device complexity.
Solution Approach 2:
The arbiter receives and processes bandwidth information from agents in advance to determine the timeslot allocation sequence before actual data transfer begins. This preliminary scheduling action allows the system to optimize bandwidth utilization by pre-configuring access patterns that match agent requirements, improving productivity without adding complexity during the data transfer operation itself.
3Ease of manufacture
If round-robin arbitration is used, then implementation simplicity is maintained, but power consumption increases
Solution Approach 1:
The patent implements periodic timeslot-based arbitration where the arbiter cycles through a determined sequence of agents based on their bandwidth requirements. This periodic scheduling pattern allows the system to maintain simple implementation through regular time-division while reducing power consumption by ensuring that agents with higher bandwidth needs receive proportionally more access opportunities, optimizing the balance between simplicity and energy efficiency.
4Productivity
If bandwidth-based sequence determination is implemented, then data transfer efficiency is improved, but arbiter complexity increases
Solution Approach 1:
The arbiter receives bandwidth information as feedback from agents and uses this information to dynamically determine the timeslot allocation sequence. This feedback mechanism allows the arbiter to adapt to varying agent requirements and optimize data transfer efficiency by allocating timeslots proportionally to bandwidth needs, managing the complexity through intelligent scheduling rather than hardware complexity.
Data Source
AI summary
Some of the embodiments of the present disclosure provide a system comprising: a shared memory unit and an arbiter that is configured to generate a clock signal, receive information regarding bandwidths of each of a plurality of agents, and determine a clock frequency or a sequence for selecting single agents among the plurality of agents to allow the single agents to transfer data in parallel from/to the shared memory unit in a single clock cycle of the clock signal, wherein the sequence is based, at least in part, on the bandwidths for each of a plurality of agents. The arbiter is also configured to cycle through the determined sequence for selecting the single agents among the plurality of agents to allow the single agents to transfer data from/to the shared memory unit in the single clock cycles.