Time-Space Switch Ring Architecture Encoding
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Solution Overview
Problem
Current time-division multiplexed (TDM) switch fabrics face challenges in increasing fabric switching capacity, line rate, and system-on-chip (SOC) integration, with existing technologies struggling to efficiently implement scalable and reliable high-speed serial links due to limitations in encoding schemes and interconnect complexity.
Innovation Solution
A time-space switch with a ring architecture and Switch Link Protocol that incorporates a two-dimensional matrix of switching circuits, pipelining, and flexible error correction, enabling scalable integration of TDM and packet fabrics in a single device with improved reliability and reduced overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 8B/10B encoding is used for serial links, then transition density and DC balance are improved, but overhead increases by 25%
Solution Approach 1:
The patent changes the encoding parameters from 8B/10B to 64B/65B, fundamentally altering the overhead ratio from 25% to approximately 1.56%. This parameter change maintains signal integrity through transition density control and DC balance while dramatically reducing overhead.
Solution Approach 2:
The patent segments the encoding process into distinct layers: 64B/65B encoding for basic overhead reduction, optional FEC for error correction, and scrambling for DC balance. This segmentation allows each layer to address specific requirements independently, optimizing overall efficiency.
2Productivity
If time-space switch capacity is increased by adding more links and higher throughput, then switching capacity is improved, but interconnect complexity increases exponentially
Solution Approach 1:
The patent introduces a temporal dimension to the switch architecture through pipelining and multi-stage processing. Instead of handling all N×N connections simultaneously in a single spatial layer, the switch distributes connections across multiple time stages, reducing the complexity of interconnects at any given moment while maintaining overall switching capacity.
Solution Approach 2:
The patent implements a nested architecture where the time-space switch contains an embedded packet switch core. This nested structure allows the system to handle both TDM and packet switching functions within a unified framework, sharing common interconnect resources and reducing overall system complexity compared to separate dedicated switches.
3Reliability
If Forward Error Correction is added on top of 8B/10B encoding, then error correction capacity is improved, but overhead increases further
Solution Approach 1:
The patent implements a universal encoding framework (64B/65B) that can operate with or without FEC depending on channel conditions. The same base encoding handles both clean and noisy channels, adding FEC only when necessary. This multi-functionality allows the system to adapt to different backplane loss characteristics without permanently incurring FEC overhead in all cases.
Data Source
AI summary
A time-space switch in a ring architecture includes input circuitry including N links each receiving M timeslots, a two-dimensional matrix of a plurality of switching circuits, the two-dimensional matrix is configured to receive from the input circuitry each of the M timeslots from the N links in a pipelined manner, and output circuitry including N links configured to receive any of the M timeslots from any of the N links from the two-dimensional matrix. The input circuitry, the two-dimensional matrix, and the output circuitry are arranged in a ring architecture therebetween. A link encoding protocol method performed in electrical circuitry includes receiving a plurality of time slots, grouping the plurality of time slots into time slot groups, performing a cyclic redundancy check between adjacent time slot groups, 64/65B encoding the time slot groups, and forward error correction encoding a plurality of 65B codewords from the 64/65B encoding.