Timestamp Control Loop Using Feedback for Clock-Domain Sync

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Communication systems face challenges in synchronizing devices with different clock domains due to indeterminate delays, leading to inaccurate timestamp transmission and potential data corruption.

Innovation Solution

A receiving device incorporates an internal timestamp control loop that adjusts its timestamp based on an initial rate and increment size, using a primary device's accurate clock to synchronize with a primary device, even when clock domains differ, by periodically receiving signals at a low frequency and adjusting the internal timestamp to minimize error.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a primary device transmits timestamps to multiple agent devices across different clock domains, then synchronization coverage is improved, but indeterministic delays increase making precise synchronization difficult

Engineering Contradiction:
Improvesynchronization coverageVSAvoidtimestamp accuracy
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent implements a feedback mechanism where agent devices monitor the arrival times of periodic timestamp signals from the primary device and adjust their internal timestamps based on measured delays. The controller compares expected arrival times with actual arrival times and modifies subsequent timestamp generation to compensate for observed delays, creating a closed-loop synchronization system that adapts to varying clock domain delays.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system dynamically adjusts timestamp parameters including the periodic transmission interval and the increment amount applied to internal timestamps. By changing these parameters based on measured performance and error accumulation, the system optimizes synchronization accuracy across different clock domains while maintaining adaptability to varying network conditions and device characteristics.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If timestamp signals are transmitted frequently between devices with different clock domains, then synchronization responsiveness is improved, but indeterministic delays increase causing greater timing errors

Engineering Contradiction:
Improvesynchronization responsivenessVSAvoidtiming accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent employs periodic transmission of timestamp signals at optimized intervals rather than continuous transmission. This periodic approach balances responsiveness with accuracy by transmitting frequently enough to maintain synchronization awareness while spacing transmissions to minimize the impact of indeterministic delays on timestamp accuracy. The period is carefully selected based on the specific clock domain characteristics.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system uses partial action by transmitting timestamp signals at a frequency that is sufficient for synchronization purposes but not maximally frequent. This partial approach avoids the diminishing returns and increased error accumulation that would result from excessive transmission frequency, while still maintaining adequate synchronization responsiveness for the application requirements.

Inventive Principle:
Principle #16Partial or excessive action

3Adaptability or versatility

If an agent device uses its own internal clock for timestamp generation, then device independence is improved, but synchronization accuracy deteriorates due to clock domain differences

Engineering Contradiction:
Improvedevice independenceVSAvoidtimestamp accuracy
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent implements dynamic timestamp adjustment where the agent device's internal timestamp generator is continuously adapted based on feedback from periodic primary device signals. The system dynamically modifies the increment amount and timing of internal timestamp generation to compensate for clock domain differences, maintaining both device independence and synchronization accuracy through adaptive control.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system performs preliminary calibration by measuring the delay characteristics between the primary device and agent device before normal operation. This preliminary action establishes baseline compensation values that are applied in advance to timestamp generation, reducing the impact of clock domain differences before they cause synchronization errors during actual data transmission.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12556295B2Timestamp control loop
Publication Date: 2026.02.17 MELLANOX TECHNOLOGIES LTD(IL)
  • US12556295B2 patent drawing
  • US12556295B2 patent drawing
  • US12556295B2 patent drawing

AI summary

A device includes a receiver including a timestamp generator to update timestamps at a first rate. The receiver is to estimate a first time for receiving a signal, wherein the signal is associated with a synchronization operation. The receiver is further to receive the signal at a second time. The receiver is further to determine a difference between the second time and the first time, wherein the difference is associated with an error of the timestamp generator of the receiver. The receiver can also adjust the first rate to a second rate at which to update the timestamps by the timestamp generator, responsive to determining the difference between the first time and the second time.