High Precision Time Stamping via Phase Detection
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Solution Overview
Problem
Current time stamping technologies in computing systems face limitations in precision due to the resolution of time stamp counters, which may not accurately capture events occurring within short time periods, especially as system speeds increase, and increasing counter frequency becomes impractical.
Innovation Solution
A method involving a reference time counter of higher accuracy and a first time counter with an updatable increment, where discrepancies are adjusted to synchronize the first time counter with the reference time counter, allowing for precise time stamping by calculating the time based on the adjusted first time counter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the counter frequency is increased to improve timestamp resolution, then the timestamp precision is improved, but it becomes impractical to increase the counter rate to the desired resolution depending on silicon technology
Solution Approach 1:
The patent replaces the mechanical approach of increasing counter frequency with a digital signal processing approach. It uses phase detection between clock signals and digital filtering to achieve high-resolution timestamps without physically increasing the counter rate, thus avoiding silicon technology constraints.
Solution Approach 2:
The patent introduces an intermediary phase detector (such as an XOR gate) that measures the phase difference between clock signals. This intermediary component enables precise timing measurement without requiring the counter to run at extremely high frequencies, bridging the gap between available hardware and desired precision.
2Measurement precision
If a typical 32-bit or 64-bit time stamp counter is used, then the device complexity is kept manageable, but the timestamp resolution is limited to the counter increment rate (e.g., 5 ns at 200 MHz)
Solution Approach 1:
The patent transitions from a single-dimension approach (increasing counter frequency) to a two-dimension approach by combining phase detection in the time domain with digital filtering. This adds a new dimension of precision without requiring proportionally higher counter frequencies or wider bit widths.
Solution Approach 2:
The patent introduces dynamic adjustment of the time stamp value based on measured phase differences. The system dynamically corrects timestamps using the phase detector and filter outputs, allowing precise timing without static increases in counter specifications.
3Measurement precision
If phase detection with an XOR gate is used to improve timestamp precision, then the timestamp accuracy is improved by accounting for latency, but the device complexity increases
Solution Approach 1:
The patent makes the phase detector and filter components multi-functional. The phase detector not only measures phase differences for timestamp correction but also provides synchronization information. The digital filter serves both to smooth phase measurements and to generate correction values, reducing the need for separate dedicated components.
Data Source
AI summary
Disclosed is a method of determining time in a digital processing system, comprising, in a present cycle of a first digital clock: accessing a reference time counter for a reference digital clock, wherein the reference time counter increments in value by a fixed amount at every cycle of the reference digital clock, the reference digital clock being of a higher accuracy than the first digital clock; accessing a first time counter for the first digital clock, wherein the first time counter increments in value by an updatable increment amount at each cycle of the first digital clock; and comparing at least one part of the reference time counter with at least one corresponding part of the first time counter. Based on the comparing, an adjustment is made to one or more attributes of the first time counter, so that first time counter at least approximates the reference time counter.