Timestamp Synchronization via Delayed Request Signals
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Solution Overview
Problem
In multi-chip interconnected systems, differences in timestamp data between chips due to asynchronous initialization of timestamp counters and varying clock sources affect the accuracy of time delay measurement, necessitating a timestamp synchronization scheme.
Innovation Solution
A chip system with a signal generating module, delay module, and signal response modules that generate and delay synchronization request signals to synchronize timestamps across chips, allowing for direct calculation of timestamp differences without complex handshake computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If each chip has its own independent timestamp counter with asynchronous initialization, then the system can operate with flexible clock sources, but timestamp data differences between chips occur affecting time delay measurement accuracy
Solution Approach 1:
The patent applies preliminary action by introducing a synchronization request signal that is generated before actual timestamp capture to prepare for coordinated timestamp recording. The request signal is sent to both chips beforehand, allowing them to capture timestamps at a predetermined synchronized moment, thereby eliminating timestamp differences without requiring complex real-time adjustments during operation.
Solution Approach 2:
The patent implements feedback through the synchronization request signal mechanism where the generating chip sends a request to both itself and the other chip, receives feedback about timestamp capture status, and uses this information to ensure both chips have captured timestamps at the same logical moment. This feedback loop ensures timestamp synchronization while maintaining flexible clock sources.
2Measurement precision
If timestamp synchronization is implemented to ensure accurate time delay measurement, then measurement precision improves, but device complexity increases due to additional synchronization mechanisms
Solution Approach 1:
The patent extracts the synchronization function from complex real-time coordination by separating the timestamp capture operation from the data processing operation. The synchronization request signal is extracted as a distinct mechanism that prepares both chips for simultaneous timestamp recording, while the actual time delay calculation can proceed independently using the captured timestamps. This extraction simplifies the overall system architecture.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of the synchronization request signal that mediates between the two chips. Instead of requiring direct complex coordination or mutual interruption, the request signal acts as an intermediary that conveys the synchronization intent to both chips, allowing them to independently capture timestamps at the correct moment without increasing overall system complexity.
3Measurement precision
If complex handshake computations are used to synchronize timestamps, then synchronization accuracy improves, but computational complexity and processing time increase
Solution Approach 1:
The patent applies the skipping principle by rushing through the synchronization process using a simple request signal mechanism instead of complex handshake computations. The synchronization request signal directly triggers timestamp capture in both chips without requiring multiple rounds of negotiation, acknowledgment, or complex timing adjustments. This skips the complicated intermediate steps of traditional handshakes while achieving accurate synchronization.
Data Source
AI summary
A chip, a chip system, and a timestamp synchronization method. The chip is configured to be in communication connection to another chip, and includes a signal generating module, a first signal response module and a first delay module. The signal generating module is configured to generate a synchronization request signal and transmit the synchronization request signal to the first signal response module and the another chip, so that the another chip records a second timestamp of the another chip in response to receiving the synchronization request signal. The first delay module is configured to perform delay processing on the synchronization request signal to obtain a delayed synchronization request signal. The first signal response module is configured to record a first timestamp of the chip in response to receiving the delayed synchronization request signal, wherein the first timestamp and the second timestamp are used for performing a timestamp synchronization operation.