Timing Analysis Device Using High-Speed I/O Terminals
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Solution Overview
Problem
Conventional timing measurement technologies in programmable logic array systems face accuracy issues due to large routing areas and limited channel numbers, leading to errors in signal measurement results.
Innovation Solution
A device and method utilizing a channel multiplexer, high-speed I/O terminals, and a sampling module to select and sample under-test signals, performing timing analysis with improved accuracy by using high-speed I/O terminals with faster logic level analyzing speeds and a calibration mechanism to compensate for channel mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delay elements connected in series are used to delay signals for timing measurement, then timing analysis can be performed, but the routing area becomes too large and measurement accuracy decreases
Solution Approach 1:
The patent extracts the timing measurement function from the basic I/O terminals and implements it using high-speed I/O terminals with dedicated sampling modules. This separation allows timing measurement to be performed with high precision without requiring large routing areas for multiple delay elements, as the high-speed terminals are specifically designed for accurate timing capture.
Solution Approach 2:
The patent changes the operating parameters by using high-speed I/O terminals with higher logic level analyzing speeds compared to basic I/O terminals. This parameter change enables accurate timing measurement without needing extensive delay elements and large routing areas, directly improving measurement precision while reducing area requirements.
2Measurement precision
If high-speed I/O terminals are used to sample signals for high accuracy measurement, then measurement accuracy improves, but the number of available channels is limited
Solution Approach 1:
The patent makes the high-speed I/O terminals serve multiple functions: they can be configured to work with different sampling modules for various timing measurement applications. The channel multiplexer enables these high-speed terminals to handle multiple signal channels sequentially, providing both high measurement accuracy and increased channel capacity through flexible configuration.
Solution Approach 2:
The patent introduces dynamic channel allocation through the channel multiplexer, which can dynamically assign high-speed I/O terminals to different channels based on measurement requirements. This dynamic configuration allows the limited high-speed terminals to effectively serve multiple channels, increasing adaptability while maintaining high measurement accuracy when needed.
3Adaptability or versatility
If multiple delay elements are used to increase channel capacity, then more channels can be measured, but routing area increases and causes measurement errors
Solution Approach 1:
The patent introduces a channel multiplexer as an intermediary device that manages the connection between multiple channels and the high-speed I/O terminals. This mediator allows multiple channels to be measured using fewer high-speed terminals without requiring large routing areas for numerous delay elements, thereby maintaining measurement accuracy while increasing effective channel capacity.
Data Source
AI summary
A device for performing timing analysis used in a programmable logic array system is provided. The device comprises first and second basic I/O terminals, a channel multiplexer, high-speed I/O terminals, a sampling module and a timing analysis module. The first basic I/O terminals receive under-test signals from an under-test unit. The channel multiplexer receives the under-test signals from the first basic I/O terminals to select at least a group of the under-test signals to be outputted to the second basic I/O terminals. The high-speed I/O terminals has a logic level analyzing speed higher than that of the first and second basic I/O terminals. The sampling module receives the group of under-test signals from the high-speed I/O terminals and samples the group of under-test signals to generate a sample result. The timing analysis module performs timing analysis and measurement according to the sample result.