Timing-Annotated Scan-Chain Testing Parallel Testbench
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Solution Overview
Problem
As integrated circuit devices become larger, scan-chain testing becomes impractical due to the time required to clock test patterns through longer scan chains, especially when testing for timing closure, as existing parallel testbenches do not account for register-to-register timing delays, leading to potential production of faulty devices.
Innovation Solution
A method and apparatus for scan-chain testing using a parallel testbench that determines and applies timing delays for each pair of adjacent registers within a single clock period, allowing each bit of the test pattern to be applied at a specific temporal offset, enabling parallel observation and comparison of outputs to expected results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan-chain testing is performed using traditional serial methods, then timing closure can be verified, but the testing time becomes impractical for large devices with long scan chains
Solution Approach 1:
The patent segments the long scan chain into multiple parallel test groups, allowing simultaneous testing of different portions of the scan chain. This segmentation enables the test bench to apply test patterns to multiple register groups in parallel, dramatically reducing the total testing time while maintaining timing closure verification capability.
Solution Approach 2:
The patent transitions from one-dimensional serial testing to multi-dimensional parallel testing by introducing temporal offset dimensions. Each parallel test group applies test patterns with specific temporal offsets that correspond to their position in the scan chain, enabling simultaneous verification of timing closure across multiple segments without interference.
2Productivity
If parallel testbench is used to reduce testing time, then testing speed improves, but register-to-register timing delays are not accounted for, leading to potential production of faulty devices
Solution Approach 1:
The patent performs preliminary determination of timing delays for each pair of adjacent registers before executing the parallel test. These pre-calculated timing delay values are stored and used to generate appropriate temporal offsets for each test group, ensuring that timing closure is verified even before the actual parallel testing begins.
Solution Approach 2:
The patent changes the temporal parameter of test pattern application by introducing specific temporal offsets for each parallel test group. These offsets are derived from the determined timing delays and are applied to synchronize the parallel testing with the actual register-to-register timing characteristics, thereby maintaining reliability while achieving speedup.
3Reliability
If timing delays are determined and applied for each register pair in parallel testing, then timing-aware testing is achieved, but the complexity of the testbench increases
Solution Approach 1:
The patent creates a simplified temporal offset model that copies the essential timing delay characteristics without requiring full replication of the complex timing analysis infrastructure. By storing predetermined timing delay values and using them to generate temporal offsets, the testbench achieves timing-aware testing while avoiding the complexity of real-time timing computation.
Solution Approach 2:
The patent introduces temporal offsets as an intermediary mechanism between the parallel testbench and the actual timing delays. These offsets act as a simplified representation that mediates the interaction between the test control logic and the physical timing characteristics, reducing the complexity burden on the testbench while maintaining timing accuracy.
Data Source
AI summary
A method of testing an integrated circuit device, that operates at a clock frequency and that has at least one scan chain that includes a plurality of registers separated by combinatorial logic, includes establishing a respective scan chain test pattern for testing the scan chain where the scan chain test pattern includes a respective bit for each register in the plurality of registers of the scan chain, determining in advance a respective timing delay for each pair of adjacent registers in the scan chain, and, within a single clock period of the clock frequency, applying, in parallel, each bit of the respective scan chain pattern to a respective register in the plurality of registers in the scan chain, each bit of the respective scan chain pattern being applied to its respective register at a respective temporal offset, within the single clock period, based on the respective timing delay.