Timing-Based Arbiter Circuit for Multi-Chip ZQ Calibration
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Solution Overview
Problem
Conventional arbiter circuits in multi-chip semiconductor devices face challenges in effectively differentiating between ZQ calibration states for chips with more than 2-chips or those using lower than 1.1V VDDQ, limiting their ability to manage simultaneous ZQ calibration requests due to voltage-based arbitration schemes.
Innovation Solution
A timing-based arbiter circuit is implemented, where each chip has unique NCH ZQ pulldown timing information stored in registers, allowing for prioritization and ensuring that higher priority chips access the shared ZQ resistor by enabling and disabling NCH ZQ pulldowns based on programmed durations and reference voltages, enabling effective ZQ calibration across multiple chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If voltage-based arbitration scheme is used, then arbitration between master chip and slave chip can be implemented, but the scheme is limited to 2-chip packages with VDDQ of 1.1V and cannot effectively differentiate between four states
Solution Approach 1:
The patent changes the arbitration parameter from voltage-based to timing-based. Each chip is assigned unique timing information stored in registers, which determines when NCH ZQ pulldown is enabled. This timing parameter differentiation allows multiple chips to be supported while maintaining clear state differentiation, resolving the limitation of voltage-based schemes that could only handle 2-chip packages with specific VDDQ requirements.
2Reliability
If only one chip can access the ZQ resistor at a time, then ZQ calibration can be performed accurately, but subsequent chips must wait until calibration is completed
Solution Approach 1:
The patent implements preliminary action by having each chip store unique timing information in registers before arbitration is needed. This pre-configured timing information determines the sequence in which chips will access the ZQ resistor, allowing the system to quickly determine arbitration outcomes without complex real-time voltage negotiations, thereby reducing total calibration time while maintaining accuracy.
3Ease of operation
If NCH ZQ pulldown is enabled for a set duration, then higher priority chips can access the ZQ resistor, but the pulldown must be disabled after the duration elapses
Solution Approach 1:
The patent implements self-service through automatic timing control. The arbiter circuit automatically enables and disables the NCH ZQ pulldown based on pre-stored timing information in registers, without requiring manual intervention or complex external control logic. The system uses the stored timing parameters to self-regulate the pulldown duration, simplifying the control mechanism while achieving effective chip prioritization.
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AI summary
Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor, a register storing timing information, and an arbiter circuit configured to determine whether the resistor is available based, at least in part, on the timing information stored in the register. The timing information stored in the register of each respective chip of the plurality of chips is unique to the respective chip among the plurality of chips.