Timing-Aware ATPG for Small Delay Defect Detection
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Solution Overview
Problem
Existing delay fault testing methods, such as the transition fault model, are inadequate in detecting small delay defects in integrated circuits due to their inability to consider actual delays through fault activation and propagation paths, leading to incomplete test sets.
Innovation Solution
The integration of timing information from Standard Delay Format (SDF) files into automatic test pattern generation (ATPG) tools to guide test generation, using weighted random methods for path selection and fault propagation, and employing fault-independent timing simulations to enhance the detection of small delay defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If transition fault model is used for test generation, then test generation is simplified and widely applicable, but small delay defects cannot be detected due to ignoring actual path delays
Solution Approach 1:
The patent performs preliminary timing analysis to compute path delays before test generation. This pre-computed timing information is then integrated into the ATPG process to guide test pattern generation, allowing the system to detect small delay defects while maintaining the efficiency of transition fault modeling.
Solution Approach 2:
The patent introduces timing information as an intermediary element between the transition fault model and the test generation process. This timing data acts as a mediator that enhances the basic transition fault approach without completely replacing it, enabling detection of small delay defects while preserving the simplicity of the original model.
2Reliability
If timing information is integrated into ATPG to detect small delay defects, then test quality improves, but test generation complexity increases
Solution Approach 1:
The patent performs timing analysis in advance to compute and store path delay information before the actual test generation process. This preliminary computation separates the complex timing analysis from the test generation itself, allowing ATPG to use pre-computed data without performing complex real-time calculations during pattern generation.
Solution Approach 2:
The patent modifies the test generation process by incorporating timing parameters (path delays) into the ATPG algorithm. These parameter changes enable the test generator to make informed decisions about which paths to target, improving test quality while managing complexity through parameter-driven guidance rather than exhaustive analysis.
3Productivity
If faults are propagated through shorter paths in transition fault testing, then test generation is more efficient, but test set cannot detect small delay defects
Solution Approach 1:
The patent changes the selection criterion for fault propagation paths by incorporating timing parameters. Instead of arbitrarily or purely structurally selecting paths, the system uses computed path delays to identify and prioritize longer paths that are more likely to reveal small delay defects, thus improving detection capability while maintaining reasonable efficiency.
Solution Approach 2:
The patent pre-computes path delays and uses this information to guide the selection of propagation paths during test generation. This preliminary timing analysis enables the system to efficiently identify which longer paths should be targeted, avoiding exhaustive exploration of all possible paths while still focusing on those most likely to detect small delay defects.
Data Source
AI summary
Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.