Timing Based Camouflage Circuit for Chip Reverse Engineering Protection
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Solution Overview
Problem
Reverse engineering of chips is challenging due to the ability to camouflage circuit functions by making their timing behavior not readily apparent from geometric layouts, which complicates the identification of circuit functions during the reverse engineering process.
Innovation Solution
Incorporating buffer cells with substantially the same geometries but differing timing behaviors, and designing clock trees and non-clock signal paths to introduce timing violations, making it difficult to determine the circuit's function from schematics and netlists prepared during reverse engineering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If buffer cells with substantially the same geometries but differing timing behaviors are used, then circuit function camouflage is improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the timing behavior parameters of buffer cells while maintaining their geometric layout. Different buffer cell types (e.g., fast, standard, slow) are selected based on timing requirements rather than geometric differences, making it difficult to determine circuit function from layout analysis alone.
Solution Approach 2:
The patent inverts the conventional approach by making buffer cells with identical geometries have different timing behaviors, rather than different geometries having different behaviors. This inversion camouflages the circuit function because reverse engineers cannot infer timing characteristics from geometric analysis.
2Difficulty of detecting and measuring
If clock trees and non-clock signal paths are designed to introduce timing violations, then circuit function camouflage is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the timing parameters of signal paths by introducing deliberate timing violations through clock tree design. This creates unpredictable timing behavior that cannot be determined from schematic analysis, as the actual timing depends on manufacturing variations and signal propagation delays.
Data Source
AI summary
In one embodiment, a chip comprising a circuit, the circuit comprising a plurality of components, wherein the circuit is adapted to perform a function that is dependent on timing behavior of the circuit, and wherein a geometry of a layout of the circuit is substantially the same as another geometry of another layout of another circuit adapted to perform another function that is dependent on different timing behavior.