External Timing Capacitor Monitoring for Multi-Chip Synchronization
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Solution Overview
Problem
In multi-chip synchronization systems, existing technologies face issues with synchronization loss due to variations in semiconductor processing, causing IC chips to detect the end of a timing period at different times, leading to incorrect system behavior and potential damage when multiple IC chips are coupled in parallel.
Innovation Solution
Implementing a system where each IC chip monitors both a rising and a falling threshold voltage on an external capacitor, with the rising threshold set below the voltage threshold minus a maximum random offset, allowing all chips to remain synchronized by detecting the capacitor's discharge once it has risen above the rising threshold and fallen below the falling threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple IC chips are coupled in parallel to increase current-carrying capability, then the power supply capability is improved, but synchronization between chips is lost due to variations in semiconductor processing causing different detection times
Solution Approach 1:
The patent introduces an intermediary mechanism (dual threshold detection system with hysteresis) that mediates between the individual chip timing circuits and the external capacitor. This intermediary system ensures that all chips respond to the same effective threshold condition, eliminating synchronization issues caused by manufacturing variations while maintaining parallel current-carrying capability.
Solution Approach 2:
The patent changes the detection parameter from a single voltage threshold to a dual threshold system with hysteresis. By implementing rising and falling thresholds separated by an offset, the system transforms the detection mechanism to be insensitive to small variations in capacitor voltage caused by manufacturing differences, thereby maintaining synchronization across multiple parallel chips.
2Device complexity
If a single voltage threshold is used for timing detection, then the circuit complexity is reduced, but manufacturing variations cause chips to detect the end of timing period at different times
Solution Approach 1:
The patent applies preliminary action by pre-establishing a hysteresis offset between the rising and falling thresholds. This pre-configured offset compensates for manufacturing variations before they can cause synchronization issues, allowing chips with different threshold characteristics to still detect the timing end simultaneously through the dual-threshold mechanism.
Solution Approach 2:
The hysteresis offset acts as a cushioning buffer that absorbs the variations introduced by manufacturing imprecision. By designing the threshold system with built-in hysteresis, the patent creates a tolerance band that prevents small manufacturing variations from causing large synchronization errors, thus cushioning the system against precision issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures that all IC chips in a parallel configuration recognize the end of a timing period simultaneously, preventing synchronization loss and maintaining correct system behavior, even with variations in voltage thresholds across chips.
Implementation Method 1
an external capacitor C1 to time an event. For example, when a fault condition such as a short occurs at a load to which power supply system 500 is coupled, IC chip 504 may need to be turned off and then on to reset the IC chip
Implementation Method 2
monitor whether the voltage threshold has been reached. Because the actual value of the voltage threshold can vary somewhat between different IC chips due to variations in semiconductor processing
Data Source
Figure 1~2B
Figure 1A
Figure 3A~3B
AI summary
A method (400) of operating the IC chip in response to an event trigger is provided. The method includes responsive to the event trigger, coupling (405) a pin to a source of constant current to charge an external capacitor coupled to the pin and monitoring (410) a capacitor voltage on the pin. If the magnitude of the capacitor voltage is greater than a rising threshold, detection (415) of a falling threshold is enabled. If the magnitude of the capacitor voltage is greater than a voltage threshold, a first response is triggered (420) and the pin is coupled (420) to the lower rail to discharge the external capacitor. If detection of the falling threshold is enabled and the magnitude of the capacitor voltage is less than the falling threshold, the first response is also triggered (425).