Timing Adjustment Circuit Startup for High-Frequency PFD Stability

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Solution Overview

Problem

Existing timing adjustment circuits, such as DLL circuits, face challenges with Phase Frequency Detector (PFD) malfunction during startup, especially at higher input clock frequencies, which hinders the generation of timing-adjusted output signals.

Innovation Solution

A timing adjustment circuit comprising a voltage-controlled delay line, a phase detector, a control voltage generation circuit, and a startup circuit that continuously changes control voltage between initial and lock voltages upon activation to synchronize clock phases and prevent PFD malfunction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the frequency of the input clock signal is increased to improve signal transmission speed, then the signal transmission speed is improved, but the operable range of the Phase Frequency Detector is narrowed causing PFD malfunction

Engineering Contradiction:

Improvesignal transmission speedVSAvoidPFD operability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The startup circuit performs preliminary action by continuously changing the control voltage during a startup period to initialize the VCDL and bring the feedback clock signal into the operable range of the PFD before normal operation begins, preventing PFD malfunction at high frequencies

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The startup circuit acts as an intermediary that temporarily modifies the control voltage to bridge the gap between initial state and stable operation, enabling the feedback clock signal to reach a state where the PFD can reliably detect phase differences even at high input frequencies

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Ensures stable multi-phase clock generation and prevents PFD malfunction even at high input clock frequencies, maintaining operational range and generating timing-adjusted output signals effectively.

Implementation Method 1

a voltage-controlled delay line receives an input clock signal and generates multi-phase clocks, a delay amount of each of the multi-phase clocks is changed according to a control voltage

Methodology Applied

Scientific EffectVoltage-controlled delay:

Implementation Method 2

The phase detector detects a phase difference between a first clock and a second clock

Methodology Applied

Scientific EffectPhase detection:

Data Source

PatentUS9172385B2Timing adjustment circuit and semiconductor integrated circuit device

Publication Date: 2015.10.27 SOCIONEXT INC

AI summary

A timing adjustment circuit includes a voltage-controlled delay line, a phase detector, a control voltage generation circuit, and a startup circuit. The voltage-controlled delay line receives an input clock signal and generates multi-phase clocks, a delay amount of each of the multi-phase clocks is changed according to a control voltage. The phase detector detects a phase difference between a first clock and a second clock, the first clock is a reference, the second clock is generated from the voltage-controlled delay line. The control voltage generation circuit generates the control voltage on the basis of the detected phase difference. The startup circuit operates for a certain period after activation, and continuously changes the control voltage between a first voltage and a second voltage.