Automated Timing Closure for Graphical Code Compilation
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Solution Overview
Problem
Existing systems for implementing high-performance applications in programmable hardware, such as FPGAs, face challenges in predicting timing and resource constraints, leading to difficult and error-prone manual analysis and testing processes during compilation from high-level graphical code to hardware implementation.
Innovation Solution
A system and method for automated analysis and feedback throughout the compilation process, allowing for optimization and modification at various stages to ensure timing accuracy and resource efficiency, using a graphical specification and constraint language to specify models of computation and constraints, and collecting information on timing and resource usage to adjust register placements and improve timing paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual analysis and testing are used during compilation from high-level graphical code to hardware implementation, then timing and resource constraints can be verified, but the process becomes difficult, tedious, and error-prone
Solution Approach 1:
The compilation system automatically performs timing analysis and generates timing reports without requiring manual intervention. The system serves itself by collecting timing information from compilation stages and automatically adjusting parameters to meet timing constraints, eliminating the need for manual analysis and testing while improving reliability
Solution Approach 2:
The system implements automated feedback loops where timing information from later compilation stages is fed back to earlier stages. This allows the system to automatically adjust high-level code parameters based on timing analysis results, resolving timing issues without manual intervention and making the compilation process easier while maintaining reliability
2Ease of manufacture
If high-level graphical code is compiled to hardware implementation, then application development is simplified, but timing and resource constraints become difficult and impossible to predict
Solution Approach 1:
The system performs preliminary timing analysis during the compilation process itself, collecting timing information at each compilation stage. This allows timing constraints to be predicted and verified automatically during compilation rather than requiring separate manual analysis, maintaining ease of development while improving timing prediction precision
Solution Approach 2:
The system replaces manual timing analysis with automated computer-based timing analysis. The compilation toolchain automatically collects timing information, generates timing reports, and adjusts parameters without human intervention, substituting mechanical manual processes with automated electronic analysis to improve timing prediction precision while maintaining ease of development
3Manufacturing precision
If automated timing analysis is performed throughout compilation, then timing accuracy is improved, but compilation complexity increases
Solution Approach 1:
The automated timing analysis is segmented into distinct compilation stages, with timing information collected and analyzed at each stage. This modular approach breaks down the complex compilation process into manageable segments, improving timing accuracy through systematic analysis while keeping the overall system complexity manageable through structured organization
Data Source
AI summary
When compiling high-level, graphical code (e.g. LabVIEW™ code) to a different representation (e.g. different software code or hardware FPGA), information relating to characteristics of the design may be collected/captured from the compilation process, and automatically provided to all the earlier stages of the compilation process to obtain more optimal results. Without automated feedback of this information, users have to manually identify, produce, and provide the feedback information, or forego the process altogether, having to assume that the tool has produced the best possible results when that may not be the case. To correct timing, failed constraints paths may be parsed and compared to delays obtained during a previous compile, and previous adjustments that didn't yield desired results may be undone. The longest delay that didn't result from an undone path may then be identified, and adjusted, and the process may be repeated until all paths are predicted to pass.