Timing Constraint Equivalence Checking for Circuit Transformations
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Solution Overview
Problem
Ensuring functional equivalence and consistency of timing constraints in circuit designs during transformations is challenging due to the use of different language constructs and the difficulty in comparing all paths, which is computationally expensive and prone to errors.
Innovation Solution
A multi-pass process for timing constraint equivalence checking that uses name mapping and a strategic path selection to compare timing relationships efficiently, reducing the need for exhaustive path enumeration by employing a multi-pass gradual refinement approach.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If exhaustive path enumeration is used to compare timing constraints, then measurement precision is improved, but productivity deteriorates due to computational expense
Solution Approach 1:
The patent segments the timing constraint verification process into multiple passes. The first pass performs a coarse comparison using representative paths, while subsequent passes progressively refine the comparison for paths that fail initial checks. This segmentation avoids exhaustive enumeration of all paths while maintaining verification accuracy.
Solution Approach 2:
The patent applies partial action by performing timing constraint comparison on a selected subset of critical paths rather than all possible paths. The multi-pass approach focuses computational resources on paths that are most likely to reveal equivalence violations, achieving sufficient verification precision without the full computational cost of exhaustive checking.
2Reliability
If all timing paths are compared to ensure equivalence, then reliability is improved, but loss of time increases due to computational complexity
Solution Approach 1:
The patent performs preliminary actions by conducting a first pass of timing constraint comparison that identifies obviously equivalent or non-equivalent cases. This preliminary filtering allows the system to avoid detailed comparison of paths that will not affect the final equivalence determination, reducing verification time while maintaining reliability.
Solution Approach 2:
The patent uses partial action by comparing only the necessary subset of timing paths across multiple passes. The method determines equivalence with high reliability by focusing on critical paths that define timing behavior, without spending excessive time on paths that do not influence the overall equivalence result.
3Manufacturing precision
If detailed path-by-path comparison is performed, then manufacturing precision is improved, but device complexity increases due to multiple comparison passes
Solution Approach 1:
The patent segments the equivalence checking process into distinct passes with increasing levels of detail. The first pass uses simplified comparison criteria, while subsequent passes apply more rigorous checks only where needed. This segmentation achieves high manufacturing precision while managing process complexity through structured progression.
Solution Approach 2:
The patent applies dynamics by making the comparison process adaptive rather than static. The multi-pass approach dynamically adjusts the level of detail and comparison stringency based on results from previous passes, focusing computational effort where it is most needed and simplifying comparisons where equivalence is already evident.
Data Source
AI summary
A first set of timing relationships may be determined in a first circuit design based on a first set of timing constraints specified for the first circuit design. A second set of timing relationships may be determined in a second circuit design based on a second set of timing constraints specified for the second circuit design. The first set of timing relationships may be compared with the second set of timing relationships to obtain a comparison result. Equivalency between the first set of timing constraints and the second set of timing constraints may be determined based on the comparison result.


