Timing Constraint Filtering for Electronic Circuit Design Debugging

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Solution Overview

Problem

Current static timing analysis (STA) tools face challenges in efficiently managing and debugging timing constraints due to the complexity of modern electronic circuit designs, leading to difficulties in navigating large constraint files, resource wastage, and the need for objective constraint generation for specific timing paths and hierarchical implementations.

Innovation Solution

A computer-implemented method that allows users to define refined filters for instance pins, library cell instances, clock pins, and nets, generating timing path constraints and performing constraint consistency analysis across multiple instantiations of a module, enabling objective constraint probing and generation in a leaner format for improved debuggability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If comprehensive timing constraints are designed for modern electronic circuit designs with multiple modes of operation, then timing analysis coverage is improved, but constraint file complexity and size increase substantially

Engineering Contradiction:
Improvetiming analysis coverageVSAvoidconstraint file complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the comprehensive timing constraints into multiple filtered subsets based on different modes of operation. The filtering mechanism divides the large constraint file into manageable portions, allowing users to analyze specific timing paths relevant to particular operational modes without being overwhelmed by the entire constraint set.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by providing different views of timing constraints tailored to specific needs. The filtering capability allows users to focus on locally relevant constraints for particular timing paths or operational modes, rather than dealing with global constraint complexity uniformly across all analysis scenarios.

Inventive Principle:
Principle #3Local quality

2Ease of operation

If designers manually manage and debug timing constraints in large constraint files, then detailed control over constraints is achieved, but time and energy consumption increase considerably

Engineering Contradiction:
Improveconstraint debugging controlVSAvoidconstraint debugging time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent implements preliminary action by pre-filtering timing constraints according to different modes of operation before the debugging process begins. This preparation step organizes constraints into ready-to-use subsets, eliminating the need for manual sifting through large constraint files during debugging and significantly reducing the time required to locate and analyze specific timing issues.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent creates filtered copies of the comprehensive constraint file for different operational modes. Instead of manipulating the entire large constraint file, users work with smaller copied subsets that contain only the relevant constraints for the current analysis context, making debugging more efficient while maintaining full control over the timing constraints.

Inventive Principle:
Principle #26Copying

3Productivity

If filtered subsets of timing constraints are generated for different modes of operation, then debuggability and navigation efficiency are improved, but additional processing steps are required

Engineering Contradiction:
Improveconstraint navigation efficiencyVSAvoidprocessing workflow complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a universal filtering mechanism that handles multiple modes of operation through a single integrated system. The same filtering infrastructure serves different filtering needs (mode-based filtering, path-based filtering, etc.), reducing the need for separate processing workflows for each type of constraint analysis while maintaining high navigation efficiency.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11347915B1System and method for objective probing and generation of timing constraints associated with an electronic circuit design
Publication Date: 2022.05.31 CADENCE DESIGN SYST INC
  • US11347915B1 patent drawing
  • US11347915B1 patent drawing
  • US11347915B1 patent drawing

AI summary

The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving an electronic design having a plurality of objects associated therewith. Embodiments may further include allowing, at a graphical user interface, a user to define at least one user-refined filter selected from the group consisting of an instance pin filter, a library cell instance filter, a clock pin filter, and a net filter. Embodiments may also include generating one or more constraints based upon, at least in part, the user-refined filter.