Timing Constraint Generation for Retimable Digital Designs
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Solution Overview
Problem
Existing logic synthesis systems face challenges in generating optimized timing constraint systems for retimable digital designs, particularly in ensuring slack equivalence, which affects the distribution and positioning of flip-flops and clocking constraints, leading to suboptimal design performance and cost.
Innovation Solution
The method involves replacing flip-flops with buffers having negative delays and breaking cycles using flip-flops with infinite or quasi-infinite clock frequency, followed by logic synthesis and retiming to achieve slack equivalence and minimize hardware cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If flip-flops are replaced with buffers having negative delays to achieve slack equivalence, then timing constraint optimization is improved, but circuit complexity increases due to the need to break cycles using flip-flops with infinite or quasi-infinite clock frequency
Solution Approach 1:
The method performs preliminary transformations on the circuit before logic synthesis by replacing flip-flops with buffers having negative delays and breaking cycles using flip-flops with infinite or quasi-infinite clock frequency. This preliminary action establishes the correct timing constraints and slack equivalence conditions upfront, allowing the subsequent logic synthesis to optimize the circuit without needing to handle complex timing relationships during the synthesis process.
Solution Approach 2:
The patent introduces intermediary elements (buffers with negative delays and artificial flip-flops with infinite clock frequency) that mediate between the original circuit and the optimized design. These intermediary components temporarily modify the circuit structure to enable proper timing constraint propagation and slack equivalence, then are removed or transformed in the final retiming step to produce the actual optimized circuit.
2Device complexity
If cycles are broken using flip-flops with infinite or quasi-infinite clock frequency, then timing constraint generation is simplified, but the number of circuit elements increases
Solution Approach 1:
The method extracts the timing constraint information from the original circuit by replacing flip-flops with buffers having negative delays. This extraction process separates the timing constraint generation from the actual circuit functionality, allowing constraints to be derived independently. The cycle-breaking flip-flops with infinite clock frequency are temporary placeholders that are removed after constraint extraction is complete.
Solution Approach 2:
The patent creates a modified copy of the original circuit where flip-flops are replaced with buffers having negative delays and cycles are broken using artificial flip-flops. This copy is used solely for generating timing constraints and slack equivalence conditions. After constraint generation is complete, the copy is discarded and the original circuit is retimed to produce the final optimized design, avoiding the need to retain the additional elements.
3Adaptability or versatility
If logic synthesis is performed before retiming, then optimization can be done independently of register distribution, but timing constraints must be carefully managed to ensure slack equivalence
Solution Approach 1:
The method performs preliminary transformations (replacing flip-flops with buffers having negative delays and breaking cycles) before logic synthesis to establish the correct timing constraints and slack equivalence conditions. This preliminary action ensures that the subsequent logic synthesis can proceed independently of register distribution while maintaining timing precision, as all timing information is already encoded in the transformed circuit structure.
Solution Approach 2:
The patent changes key parameters of the circuit by replacing flip-flops with buffers having negative delays and introducing flip-flops with infinite or quasi-infinite clock frequency to break cycles. These parameter changes transform the circuit into a form where timing constraints can be properly propagated and slack equivalence can be achieved, allowing logic synthesis to optimize independently of register distribution while maintaining timing precision.
Data Source
AI summary
A method for generating timing constraint systems, where the constrained object is a digital circuit., is provided, where the constraints are generated for the use of a digital logic optimization (synthesis) tool. The synthesis tool is used to optimize the circuit, under the applied constraints, so that the circuit exhibits certain desirable timing properties, while at the same time minimizing hardware cost and various other properties. The particular class of timing constraints generated by the disclosed invention is useful when the circuit is to be retimed after optimization. Typically, the joint use of the described invention and retiming results in improvements in the overall cost/performance tradeoff curve of the design. The invention comprises a method that comprises the following steps: (1) the flip-flops of the design are replaced with buffers having a negative delay whose magnitude is approximately the desired clock cycle time of the design; and (2) cycles in the design are broken using flip-flops having an infinite or quasi-infinite clock frequency. Following optimization by the synthesis tool, the temporary changes can be reverted, and retiming performed on the circuit.