Timing Constraint Verification for Ported ASIC and SoC Netlists
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Solution Overview
Problem
Design porting of application-specific integrated circuits (ASIC) and System on Chips (SoC) across different technology nodes faces challenges in validating timing constraints, leading to potential mismatches in attribute compatibility and performance, which can result in design failures and require extensive engineering tuning.
Innovation Solution
The attribute-point-based timing constraint verification methodology involves extracting and comparing valid timing paths and critical attributes between a golden circuit design and a target circuit design, identifying mismatches, and making necessary design updates to ensure compatibility and meet performance goals, using static timing analysis (STA) and point-based reporting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If design porting is performed across technology nodes, then design time is reduced through re-use of circuit blocks, but timing constraint validation becomes challenging and may lead to attribute compatibility mismatches
Solution Approach 1:
The patent performs preliminary extraction of timing paths and attributes from the source design before porting, and conducts preliminary verification by comparing these extracted attributes against the target design's timing constraints. This advance preparation identifies potential compatibility issues before full implementation, reducing the risk of timing failures while maintaining design reuse benefits.
Solution Approach 2:
The patent introduces an intermediary verification process that acts as a mediator between the source design attributes and target design constraints. This intermediary layer extracts timing paths, compares attributes, and validates compatibility, serving as a bridge that ensures reliable timing constraint satisfaction during technology node porting.
2Reliability
If traditional timing verification methods are used after design porting, then potential timing issues can be detected, but extensive engineering tuning and iteration are required
Solution Approach 1:
The patent performs timing attribute extraction and verification before final design implementation, identifying potential timing issues in advance. By extracting timing paths and comparing attributes preliminarily, the method detects problems early, reducing the need for extensive post-porting engineering tuning and iteration.
Solution Approach 2:
The patent implements a feedback mechanism where extracted timing attributes from the source design are compared against target design constraints, and mismatches are identified and reported. This feedback loop enables targeted corrections rather than extensive trial-and-error tuning, reducing iteration time while maintaining reliable timing verification.
3Reliability
If comprehensive timing constraint validation is performed, then design compatibility is ensured, but verification complexity and resource requirements increase
Solution Approach 1:
The patent segments the comprehensive timing verification process into distinct components: extraction of timing paths, extraction of timing attributes, comparison of attributes, and identification of mismatches. This segmentation breaks down complex verification into manageable steps, reducing verification complexity while maintaining thorough compatibility checking.
Solution Approach 2:
The patent extracts specific timing paths and attributes from the source design netlist, separating the essential timing characteristics from the complete design. By extracting only the relevant timing attributes needed for verification, the method reduces verification complexity while ensuring comprehensive design compatibility through targeted attribute comparison.
Data Source
AI summary
Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA). The attribute mismatch is provided for further design or timing constraint modifications and/or updates using this approach, particularly timing formal verification, at the target technology in order to enable efficient design timing sign-off based on ported netlists and synthesis design constraints (SDC).