Automatic Timing Constraint Promotion in SoC Design
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Solution Overview
Problem
The development of timing constraints for system-on-a-chip (SoC) designs is a manual, tedious, and error-prone process, leading to delays and failures due to the lack of efficient automated solutions, especially with increasing clock complexity and operational modes.
Innovation Solution
A method for automatically promoting timing constraints from lower level blocks to upper level blocks in the Synopsys Design Constraint format, using software tools to extract and stitch primary clocks with generated clocks, while maintaining the original timing intent, and allowing for both isolation and integration modes to align or preserve block-level timing with top-level timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual timing constraint development is used, then timing constraints can be created for each hierarchical block, but the process becomes tedious and time-consuming
Solution Approach 1:
The system automatically extracts timing constraints from lower-level block SDC files and promotes them to upper-level blocks without requiring manual intervention. The tool self-manages the extraction, transformation, and integration of timing constraints across hierarchical levels, eliminating the need for designers to manually create top-level constraints from bottom-level block constraints.
Solution Approach 2:
The manual mechanical process of copying and adapting timing constraints across hierarchy levels is replaced by an automated software system. The tool reads SDC files, extracts clock definitions and timing constraints, generates appropriate promote_sdc commands, and integrates them into the top-level design automatically.
2Reliability
If manual timing constraint promotion is used, then timing constraints can be adapted to different hierarchical levels, but the process is error-prone
Solution Approach 1:
The system provides feedback by automatically validating and verifying timing constraint promotion. It checks for conflicts between promoted constraints and existing top-level constraints, identifies issues with clock relationships, and ensures that promoted constraints are compatible with the target hierarchical level before integration.
Solution Approach 2:
The software tool acts as an intermediary between lower-level block SDC files and top-level design constraints. It extracts timing information from block-level files, transforms them into appropriate format for top-level integration, and mediates the promotion process by generating promote_sdc commands that safely integrate constraints without manual intervention.
3Reliability
If timing constraints are developed bottom-up, then block-level timing can be optimized, but top-level timing constraints become complex and difficult to manage
Solution Approach 1:
The system segments timing constraint management by maintaining separate SDC files for each hierarchical block while automatically extracting and promoting only the necessary timing information to upper levels. This segmentation allows block-level optimization without requiring manual management of all constraints at the top level.
Solution Approach 2:
The tool extracts only the essential timing constraints from lower-level block SDC files and promotes them to upper levels. It selectively extracts clock definitions, timing relationships, and critical path information while filtering out block-specific details that are not needed at higher hierarchical levels, thereby reducing top-level complexity.
Data Source
AI summary
A computer-implemented method of promoting timing constraints in an electronic design automation process of a chip is provided. A method of promoting a lower level block's timing constraint to an upper level block by providing an option to preserve the timing intent of the lower level block at the same time, or to modify the timing constraint such that the block level timing is in context to the top level block timing is provided. The method implements automatic promotion of timing constraint in different modes as an integration mode; an isolation mode and combination thereof, wherein the integration mode is independent of SDCs; and the isolation mode is based on the input SDCs. A method of automatically promoting constant values that are defined through a set_case_analysis command in the SDC file is further provided.