Timing Control Circuit for High-Speed Bus Access to Low-Speed Peripherals
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Solution Overview
Problem
Semiconductor devices face performance degradation due to the significant gap between high-speed and low-speed bus operating frequencies, leading to slow interrupt response and increased power consumption when trying to improve access speed to low-speed circuit blocks from high-speed blocks.
Innovation Solution
A timing control circuit is introduced between the high-speed CPU and low-speed peripheral circuits, allowing data transfer in synchronization with the high-speed clock signal for reading and low-speed clock signal for writing, enabling high-speed bus access without significantly increasing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-speed bus interface is installed in peripheral circuits to improve access speed, then access speed improves, but power consumption increases significantly
Solution Approach 1:
A timing control circuit is introduced as an intermediary component between the high-speed bus and low-speed peripheral circuits. This timing control circuit synchronizes data transfer timing, allowing the peripheral circuits to operate at low speed while the bus operates at high speed, thus improving access speed without requiring high-speed interfaces in power-consuming peripheral circuits
Solution Approach 2:
The patent applies different operating speeds to different parts of the system: the bus operates at high speed while peripheral circuits operate at low speed. The timing control circuit locally manages the speed difference by controlling data transfer timing, allowing each component to operate optimally without forcing all components to high speed
2Reliability
If the CPU stalls to complete low-speed bus cycles, then data integrity is maintained, but system performance degrades
Solution Approach 1:
The timing control circuit dynamically adjusts the timing of data transfer between the high-speed bus and low-speed peripheral circuits. Instead of static stalling, the system dynamically synchronizes data transfer to match peripheral circuit readiness while maintaining high bus utilization, thus preserving data integrity without prolonged stalls
Solution Approach 2:
The timing control circuit uses periodic clock signals to coordinate data transfer. By aligning data transfer with periodic clock cycles of the peripheral circuits, the system ensures data integrity is maintained through regular synchronization points while keeping the CPU busy with other tasks between transfers
3Adaptability or versatility
If multiple peripheral circuits are mounted on the chip, then system functionality increases, but total power consumption increases when high-speed interfaces are added
Solution Approach 1:
The timing control circuit serves multiple peripheral circuits simultaneously, providing a universal interface solution. Instead of adding high-speed interfaces to each individual peripheral circuit, the single timing control circuit handles timing for all peripheral circuits, enabling multiple circuits to function efficiently without proportionally increasing power consumption
Data Source
AI summary
In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.