Timing Control Circuit for Asynchronous Memory Data Transfer
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Solution Overview
Problem
Existing memory devices face challenges in accurately controlling timing parameters, such as CAS Latency and row-to-column delay, especially when accessing synchronous memory modules through asynchronous interfaces, which can lead to data integrity issues and failed transactions.
Innovation Solution
A timing control circuit and method that dynamically adjusts a tracking clock signal based on various latency parameters within the memory module, allowing for precise timing control independent of the external clock signal, thereby ensuring correct data access and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous interface is used to access synchronous memory module, then interface flexibility and adaptability are improved, but timing control precision deteriorates leading to data integrity issues
Solution Approach 1:
The patent introduces a timing control circuit as an intermediary component between the asynchronous interface and the synchronous memory module. This circuit generates internal timing signals (such as column selection signals) that mediate the interaction between the asynchronous external interface and the synchronous memory operations, thereby maintaining timing precision while preserving interface flexibility.
Solution Approach 2:
The timing control circuit segments the timing control function from the main memory operations. By separating the generation of column selection signals and other timing-critical signals into a dedicated circuit module, the patent ensures that timing precision is maintained independently from the asynchronous interface operations.
2Reliability
If external clock signal is used for timing control, then synchronization with external controller is improved, but reliability deteriorates when external clock is unavailable
Solution Approach 1:
The timing control circuit implements self-service by generating its own internal timing signals based on received command signals, rather than relying exclusively on an external clock signal. The circuit can autonomously generate column selection signals and other timing signals based on the asynchronous command interface, ensuring operation independence while maintaining synchronization when needed.
3Device complexity
If timing parameters are fixed, then design simplicity is improved, but adaptability to different latency conditions deteriorates
Solution Approach 1:
The timing control circuit implements dynamic timing parameter adjustment by generating internal timing signals adaptively based on the specific latency conditions and memory operations. The circuit can adjust the timing of column selection signals and other critical signals dynamically according to the actual memory state and operation requirements, rather than using fixed timing parameters.
Data Source
AI summary
A timing control circuit for use in a memory module includes: a clock generation circuit and a data queue. The clock generation circuit is configured to generate one or more delayed versions of an external clock signal and select one of the external clock signal and the one or more delayed versions of the external clock signal to generate a tracking clock signal according to a write latency count satisfaction indication signal and a row-to-column delay end indication signal. The data queue is configured to queue input data according to the external clock signal and generate an output data signal by de-queuing the queue data according to the tracking clock signal. Specifically, the output data signal and the tracking clock signal are utilized to perform a write operation within the memory module in response to an external write command.