Timing Control Circuit for Fast Access to Low-Speed Peripherals
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Solution Overview
Problem
Semiconductor devices face performance degradation due to the significant gap between high-speed and low-speed bus operating frequencies, leading to slow interrupt response and increased power consumption when trying to improve access responsiveness to low-speed circuit blocks.
Innovation Solution
A timing control circuit is introduced between the high-speed CPU and low-speed peripheral circuits, allowing data transfer in synchronization with the high-speed clock signal for reading and low-speed clock signal for writing, enabling high-speed bus access without significantly increasing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-speed bus interface is installed in peripheral circuits to improve access speed, then access speed is improved, but power consumption significantly increases
Solution Approach 1:
The system is segmented into high-speed CPU domain and low-speed peripheral circuit domain, with each domain operating at its own clock frequency. The timing control circuit acts as an interface layer that translates between the two domains, allowing fast access without forcing all peripheral circuits to operate at high speed continuously.
Solution Approach 2:
The timing control circuit dynamically adjusts the clock frequency based on access requirements. When the CPU needs to access peripheral circuits, the timing control circuit operates at high speed to translate requests; when no access is needed, peripheral circuits continue operating at low speed to save power.
2Stability of the object's composition
If the CPU stalls to wait for low-speed bus cycle completion, then timing synchronization is maintained, but system performance degrades
Solution Approach 1:
The timing control circuit serves as an intermediary between the high-speed CPU and low-speed peripheral circuits. It translates CPU access requests into appropriately timed signals for the peripheral circuits, eliminating the need for CPU stalling while maintaining proper timing synchronization through buffer circuits and control logic.
3Adaptability or versatility
If a bus bridge circuit is used to couple high-speed and low-speed buses, then communication between different speed domains is enabled, but access speed remains limited by the low-speed bus
Solution Approach 1:
The access path is segmented into three parts: high-speed CPU domain, timing control circuit interface layer, and low-speed peripheral circuit domain. This segmentation allows the CPU and timing control circuit to operate at high speed while only the peripheral circuits operate at low speed, improving overall access speed compared to a simple bus bridge.
Solution Approach 2:
The traditional mechanical bus bridge coupling is replaced with a more sophisticated timing control circuit that uses clock signal generation, buffer circuits, and control logic to translate between speed domains. This substitution enables asynchronous operation and eliminates the speed limitation imposed by the low-speed bus on the entire system.
Data Source
AI summary
To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.Ina data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.