Timing Controller Bit Capture Circuit for Display Data Transmission

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Solution Overview

Problem

Existing display devices face challenges in reducing the number of bits in sub-pixel data received by the digital-to-analog converter (DAC) of a source driver, affecting the quality of the human-machine interface in consumer electronics.

Innovation Solution

A timing controller with a bit capture circuit and a gear position signal generation circuit is used to capture and process sub-pixel data, determining a gear position signal that adjusts gamma voltages, thereby reducing the number of bits required for the DAC to transmit source driving signals to a display panel.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the number of bits in sub-pixel data is reduced for DAC input, then the complexity of the data transmission system is reduced, but the display quality and precision may deteriorate

Engineering Contradiction:
Improvedata transmission system complexityVSAvoiddisplay quality
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent segments the 10-bit sub-pixel data into two parts: the upper 6 bits are transmitted directly to the DAC, while the lower 4 bits are used to generate a gear position signal. This segmentation allows the system to reduce transmission bit width while preserving display quality through the gear position signal mechanism.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary processing of the sub-pixel data by extracting the lower 4 bits to generate the gear position signal before DAC conversion. This preliminary action enables the system to prepare compensation information in advance, ensuring display quality is maintained despite reduced transmission bits.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the number of bits in sub-pixel data is reduced, then the data transmission efficiency is improved, but the precision of gamma voltage adjustment may worsen

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoidgamma voltage adjustment precision
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent introduces the gear position signal as an intermediary between the reduced-bit data and the gamma voltage generation. The gear position signal (derived from lower 4 bits) acts as a mediator that provides the gamma voltage generation circuit with precise positioning information, maintaining adjustment precision despite reduced data bit width.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the parameter representation by converting the lower 4 bits into a gear position signal that indicates specific voltage levels or ranges. This parameter transformation allows the system to convey precise gamma voltage adjustment information using fewer bits in the main data stream.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If bit capture circuit and gear position signal generation circuit are added, then the sub-pixel data processing capability is improved, but the circuit complexity increases

Engineering Contradiction:
Improvesub-pixel data processing capabilityVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent designs the bit capture circuit and gear position signal generation circuit to perform multiple functions: they extract bits for gear position signaling, enable gamma voltage adjustment, and maintain compatibility with existing DAC structures. This multi-functionality justifies the added circuit complexity by providing enhanced processing capabilities.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements a nested structure where the gear position signal generation circuit is integrated within the timing controller, which itself is part of the display driver system. The bit capture functionality is nested within the data processing pipeline, allowing these additional circuits to be incorporated without fundamentally restructuring the entire system.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS11087660B2Timing controller and operating method thereof
Publication Date: 2021.08.10 HIMAX TECH LTD
  • US11087660B2 patent drawing
  • US11087660B2 patent drawing
  • US11087660B2 patent drawing

AI summary

A timing controller and an operating method are provided. The timing controller includes a bit capture circuit and a gear position signal generation circuit. The bit capture circuit is configured to capture a first part bit from each of a plurality of original sub-pixel data of a video stream. The gear position signal generation circuit determines a gear position signal related to a current frame according to the first part bits. The gear position signal is provided to a gamma voltage generation circuit of a source driver such that the gamma voltage generation circuit changes a plurality of gamma voltages according to the gear position signal.