Timing Controller Power-Down During Display Blank Periods

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Solution Overview

Problem

Existing timing controllers and display devices experience unnecessary power consumption during blank periods due to functional blocks and memory devices remaining active when they do not need to operate.

Innovation Solution

A timing controller with a blank period detection circuit and power-down control signal generation circuit to deactivate functional blocks and memory devices during blank periods, using control signals from an external system to minimize power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If functional blocks and memory devices remain active during blank period, then operational readiness is maintained, but power consumption increases unnecessarily

Engineering Contradiction:
Improveoperational readinessVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies periodic action by switching functional blocks and memory devices between active and power-down states based on the display period and blank period cycles. The controller activates these components during display periods when image data processing is needed, and deactivates them during blank periods when no processing is required, creating a rhythmic on-off pattern that reduces power consumption while maintaining operational readiness when needed.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent implements dynamics by making the operational state of functional blocks and memory devices changeable rather than static. The controller dynamically adjusts the power state of these components based on real-time detection of blank periods, transitioning from an always-active state to a state that adapts between active and power-down modes, thereby optimizing power consumption without compromising functionality.

Inventive Principle:
Principle #15Dynamics

2Use of energy by moving object

If functional blocks are deactivated during blank period, then power consumption is minimized, but detection of blank period requires additional circuits

Engineering Contradiction:
Improvepower consumptionVSAvoidcircuit structure
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent applies universality by making the existing controller perform multiple functions: it not only controls the display timing but also detects blank periods and generates power-down control signals. By integrating these additional functions into the existing controller structure, the patent avoids adding separate dedicated circuits for blank period detection, thereby minimizing power consumption without significantly increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements self-service by enabling the controller to automatically detect blank periods and generate appropriate power-down control signals without external intervention. The controller monitors its own operational state and autonomously decides when to activate or deactivate functional blocks and memory devices, eliminating the need for additional control circuits and reducing overall system complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP4632719A1Timing controller for minimizing power consumption during blank period
Publication Date: 2025.10.15 LX SEMICON CO LTD
  • EP4632719A1 patent drawingFigure 1
  • EP4632719A1 patent drawingFigure 2
  • EP4632719A1 patent drawingFigure 3

AI summary

The present invention proposes a timing controller capable of minimizing power consumption during a blank period by disabling the operation of a corresponding functional block or a memory device included in the corresponding block during the blank period. The timing controller comprises: a blank period detection circuit for generating a blank period detection signal by using a clock signal and a gate drive signal; and a functional block group comprising a plurality of functional blocks carrying out operations in accordance with a display period and a blank period in response to the gate driving signal, a data driving signal, and the blank period detection signal.